Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-08-25
2001-10-16
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S189090, C365S230060
Reexamination Certificate
active
06304488
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and in particular, the present invention relates to isolation of defective portions from remaining portions of a non-volatile semiconductor memory device using a current limiting negative switch circuit.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For speed of operation, erasures of non-volatile memory devices, such as flash memory devices, are generally carried out in blocks rather than individual memory cells. As such, a defect in one portion of the block may cause the entire block to be unusable. Global failures of an entire block may not be repairable through redundancy. To avoid such global failures, a defective portion of the memory block must generally be isolated to some degree from remaining portions of the memory block during an erase operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate methods and circuits for isolating defective portions in non-volatile flash memory devices.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. The various embodiments of the invention provide for selective coupling of a negative potential node, such as the output of a negative charge pump, to a load, such as a potential node supplying a word line driver in a non-volatile memory device.
Erase operations in non-volatile memory devices are often carried out in blocks rather than individual cells. Such block erase operations generally apply a negative erase voltage from a negative potential node to each word line of the memory block. If a word line is shorted to a bit line, the negative erase voltage may be incapable of reaching the levels necessary to achieve erasure of the memory block. With the inability to effectively erase an entire block of memory cells, the memory device may be commercially unacceptable. Various embodiments described herein utilize a current limiting negative switch circuit to decouple a defective portion of a memory block, i.e., a portion containing such a shorted word line, from the negative potential node while permitting coupling of at least a portion of the remaining, non-defective word lines to the negative potential node.
For one embodiment, the invention provides a negative switch circuit. The negative switch circuit includes a first electrical path coupled between an input and an output of the negative switch circuit and having a first switch, a second electrical path in parallel with the first electrical path and having a second switch and a third switch coupled in series, and a feedback controller having an input coupled to the output of the negative switch circuit. The first switch is coupled to receive a first control signal, the second switch is coupled to receive a second control signal, and the third switch is coupled to receive a feedback control signal from an output of the feedback controller.
For another embodiment, the invention provides a negative switch circuit. The negative switch circuit includes a first electrical path coupled between an input and an output of the negative switch circuit and a second electrical path coupled in parallel with the first electrical path. The first electrical path is adapted to present an open circuit between the input and the output of the negative switch circuit in response to a first state of a first control signal and to present a closed circuit between the input and the output of the negative switch circuit in response to a second state of the first control signal. The second electrical path is adapted to present an open circuit between the input and the output of the negative switch circuit in response to a first state of a second control signal and to permit a closed circuit between the input and the output of the negative switch circuit in response to a second state of the second control signal. The second electrical path is further adapted to present an open circuit between the input and the output of the negative switch circuit in response to a first state of a feedback control signal regardless of the state of the second control signal and to permit a closed circuit between the input and the output of the negative switch circuit in response to a second state of the feedback control signal when the second control signal is in the second state.
For a further embodiment, the invention provides a method of selectively coupling a negative potential node to a load. The method includes coupling the negative potential node to the load during a first period, decoupling the negative potential node from the load during a first phase of a
Abedifard Ebrahim
Roohparvar Frankie F.
Fogg Slifer & Polglaze, P.A.
Leffert Thomas W.
Mai Son
Micro)n Technology, Inc.
LandOfFree
Current limiting negative switch circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Current limiting negative switch circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current limiting negative switch circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2601751