Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1981-04-16
1982-08-31
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307442, 307448, 307450, 307473, H03K 19003, H03K 19007, H03K 19094, H03K 1716
Patent
active
043474470
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to driver circuits in logic applications and more particularly pertains to such driver circuits which must have a current limited output.
BACKGROUND ART
In certain logic circuits an output data state is produced at an output terminal. The output terminal is then connected to deliver the output signal to other circuit elements. The output terminal is typically driven to high and low voltage states. If the output terminal should become grounded when the circuit is attempting to drive it to a high voltage state there may be a heavy current flow through the driving circuit. If no means are provided for limiting current flow through the output terminal, the surge of current can frequently be sufficient to damage the driving circuit. The provision of a current limiting resistor, however, has the disadvantage that it slows the driver circuit in driving the output terminal to the desired voltage state.
In view of the above problems there exists a need for a current limiting driver circuit in which the output terminal can be rapidly driven to the highest voltage state required while at the same time having a limitation on the current which can be transmitted through the output terminal to prevent damaging the driver circuit or related circuits.
SUMMARY OF THE INVENTION
In a selected embodiment of the present invention a current limiting circuit is described which drives an output node to selected logic states in response to an input signal. A driver transistor is included in the circuit and has the gate terminal thereof connected to receive a control signal, the drain terminal thereof connected to a power terminal and the source terminal thereof connected to the output node. Circuitry is connected between the gate and source terminals of the driver transistor to limit the maximum voltage difference therebetween to a predetermined voltage thereby limiting the current flow through the driver transistor. In a further aspect of the present invention circuitry is provided to isolate the output node to leave it in a high impedance condition.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following Description taken in conjunction with the accompanying Drawings in which:
FIG. 1 is a schematic illustration of a first embodiment of a current limiting driver circuit and
FIG. 2 is a schematic illustration of a second embodiment of a current limiting driver circuit.
DETAILED DESCRIPTION
A first embodiment of a current limiting driver circuit in accordance with the present invention is illustrated in FIG. 1 and designated generally by the reference numeral 10. Circuit 10 includes a depletion mode pull-up transistor 12 which has the gate and source terminals thereof connected to a node 14. The drain terminal of transistor 12 is connected to a first power terminal V.sub.cc.
A pull-down transistor 16 has the gate terminal connected to receive a logic level input signal .phi..sub.1. The drain terminal of transistor 16 is connected to node 14 and the source terminal of transistor 16 is connected to ground.
A pull-down transistor 17 has the gate terminal thereof connected to receive a logic level input signal .phi..sub.2. The drain terminal of transistor 17 is connected to node 14 and the source terminal is connected to ground.
A transistor 18 has the gate and drain terminals thereof connected to node 14. A transistor 20 has the gate and drain terminals thereof connected to the source terminal of transistor 18. A transistor 22 has the gate and drain terminals thereof connected to the source terminal of transistor 20. The source terminal of transistor 22 is connected to an output node 24 which is in turn connected to an output pin 26. Output data is transmitted through the pin 26.
A driver transistor 28 has the gate terminal thereof connected to node 14, the drain terminal thereof connected to the power terminal V.sub.cc and the source terminal thereof connected to the outpu
REFERENCES:
patent: 3651340 (1972-03-01), Cliff
patent: 3906255 (1975-09-01), Mensch, Jr.
patent: 3913026 (1975-10-01), Koehler
patent: 4065678 (1977-12-01), Reese et al.
patent: 4096398 (1978-06-01), Khaitan
patent: 4275313 (1981-06-01), Boll et al.
Homan, "FET Depletion Load Push-Pull Logical Circuit"; IBM Tech. Discl. Bull.; vol. 18, No. 3, pp. 910-911; 8/1975.
Anagnos Larry N.
Mostek Corporation
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