Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-09-05
2003-06-03
Vu, Bao Q. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S303000, C323S282000
Reexamination Certificate
active
06573693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrical device having an output transistor for limiting an input current to produce an output current and a bypass capacitor connected to the output side of the output transistor.
2. Description of the Prior Art
Since its debut some time ago, the USB (universal serial bus) has been receiving much attention as an interface bus for connecting a host computer, such as a personal computer, to a peripheral device, such as a floppy disk drive, printer, scanner, or the like. Peripheral devices equipped with a USB (hereinafter such devices will be referred to as “USB devices”) make it possible to use a single unified interface for a plurality of peripheral devices that have conventionally been requiring different interfaces.
A USB device is connected to a host computer by way of a USB cable. For easy connection and convenience, the USB cable includes not only signal lines by way of which signals are exchanged between the USB device and the host computer, but also power supply lines by way of which electric power is supplied from the host computer to the USB device.
Moreover, the USB device is equipped with a high side switch circuit for making “softer” (less abrupt) the rising of the rush current that occurs when the USB device is plugged into the host computer, and thus the power supply lines of the USB cable are connected through the high side switch circuit to the internal circuits of the USB device. The high side switch circuit is configured as a current limiter that limits the supply current supplied from the host computer to a predetermined level before it is fed to the internal circuits.
FIG. 10
is a circuit diagram showing an example of the configuration of a conventional high side switch circuit. As this figure shows, the high side switch circuit
10
′ is provided with an output transistor Q
1
that limits the supply current supplied from outside the device to produce an output current to be output to the internal circuits of the device. The figure shows an example in which a P-channel MOS transistor is used as the output transistor Q
1
.
The supply current fed from outside the device is fed in via an input terminal T
1
. The input terminal T
1
is connected through a resistor R
1
to the source (S) of the transistor Q
1
, and is also connected through serially connected resistors R
2
and R
3
and then through a constant-current source
11
to ground. The current that is to be fed to the internal circuits of the device is fed out via an output terminal T
2
. The output terminal T
2
is connected to the drain (D) of the transistor Q
1
, and is also connected through a bypass capacitor C
1
to ground.
Moreover, the high side switch circuit
10
′ is provided with an operational amplifier A
1
as a means for controlling the gate voltage of the transistor Q
1
. The non-inverting input terminal (+) of the operational amplifier A
1
is connected to the node between the resistors R
2
and R
3
, and its inverting input terminal (−) is connected to the source (S) of the transistor Q
1
. The output terminal of the operational amplifier A
1
is connected to the gate (G) of the transistor Q
1
.
Now, how this high side switch circuit
10
′ configured as described above operates will be described. The operational amplifier A
1
amplifies the voltage difference between the reference voltage V
ref
fed to its non-inverting input terminal (+) and the comparison voltage V
adj
fed to its inverting input terminal (−), and thereby produces the gate voltage of the transistor Q
1
.
For example, when a large current flows through the transistor Q
1
, the voltage drop across the resistor R
1
becomes greater. Thus, the comparison voltage V
adj
drops, and the output voltage of the operational amplifier A
1
becomes higher. As a result, the voltage difference between the gate and source of the transistor Q
1
becomes smaller, and thus the transistor Q
1
now permits only a smaller current to flow through it. By contrast, when the current that flows through the transistor Q
1
becomes smaller, and thus the comparison voltage V
adj
becomes higher, the output voltage of the operational amplifier A
1
becomes lower. As a result, the voltage difference between the gate and source of the transistor Q
1
becomes greater, and thus the transistor Q
1
now permits a larger current to flow through it.
In this way, the high side switch circuit
10
′ is a circuit that limits the output current I
out
that flows through the transistor Q
1
in such a way that the comparison voltage V
adj
is kept equal to the predetermined reference voltage V
ref
. In this high side switch circuit
10
′ configured as described above, setting the reference voltage V
ref
higher results in making the target value of the output current I
out
smaller and, by contrast, setting the reference voltage V
ref
lower results in making the target value of the output current I
out
greater. Conventionally, the reference voltage V
ref
is fixed at a voltage determined on the basis of the ultimate target value of the output current I
out
to be fed to the internal circuits of the device.
FIG. 11
is a time chart showing the behavior of the input voltage V
in
and the output current I
out
in the high side switch circuit
10
′. As solid lines in this figure indicate, when an input voltage V
in
is applied to the input terminal T
1
of the high side switch circuit
10
′, an output current I
out
starts flowing through the bypass capacitor C
1
. Here, the rising of the output current I
out
that charges the bypass capacitor C
1
is made softer to a certain degree by the high side switch circuit
10
′.
The peak value of the current that charges the bypass capacitor C
1
and the time needed to charge it are determined by the capacitance of the bypass capacitor C
1
and the reference voltage V
ref
of the high side switch circuit
10
′ (i.e. the target value of the output current I
out
). In
FIG. 11
, what the solid lines indicate is the behavior observed when the bypass capacitor C
1
is the only load that is connected to the output terminal T
2
, and accordingly, when the charging of the bypass capacitor C
1
is complete, the output current I
out
drops to zero. In a case where another load circuit is connected to the output terminal T
2
, however, a current commensurate with the load continues to flow even after the completion of the charging of the bypass capacitor C
1
(as a dash-and-dot line in the figure indicates).
The high side switch circuit
10
′ configured as described above does serve, indeed, to limit the output current I
out
fed out via the output terminal T
2
through feedback control as described above and thereby make softer to a certain degree the rush current that occurs when the USB device is plugged into the host computer. Thus, it is possible to prevent to a certain extent the power supply circuit provided in the host computer from being overloaded. In addition, the output current I
out
from the high side switch circuit
10
′ is first accumulated in the bypass capacitor C
1
before it is fed out. This helps make smooth and reduce the noise components in the current that is fed to the internal circuits of the USB device.
However, in the conventional high side switch circuit
10
′, the bypass capacitor C
1
is given a fixed capacitance that is so set that the peak value of the current that charges it and the time needed to charge it comply with the USB standard and the specifications of the ICs used internally. That is, it is impossible to adjust the waveform of the current that charges the bypass capacitor C
1
according to the power supply performance of the power supply circuit provided in the host computer, the characteristics of the USB cable, and other factors (i.e. to adjust it, for example, in such a way that the peak value of the current that charges the bypass capacitor C
1
and the time needed to charge it comply with the USB stan
LandOfFree
Current limiting device and electrical device incorporating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Current limiting device and electrical device incorporating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current limiting device and electrical device incorporating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3115261