Current limiting clamp circuit

Details Current limiting clamp circuit Current limiting clamp circuit

1991-05-06

1993-01-26

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 307568, 323313, G05F 316, G05F 320

Patent

active

051824680

ABSTRACT:
A current limiting clamp circuit for providing a clamped voltage at a node and including a P-type MOS transistor and several N-type MOS transistors which are connected in series between the drain of the P-type MOS transistor and ground, with one of the N-type transistors having its gate and drain connected to the drain of the P-type transistor, and having its source connected to the node. In another embodiment, the current limiting clamp circuit includes a pair of P-type transistors and several N-type transistors, with one of the P-type transistors having its source connected to a power supply, its gate connected to ground and its drain connected to the source of the other P-type transistor which has its gate and drain connected to the node.

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IBM Technical Disclosure Bulletin (vol. 31 No. 1, Jun. 1988) pp. 21-23, "Device Parameter Independent Delay Circuit".

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