Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-05-28
2001-05-29
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000
Reexamination Certificate
active
06239733
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic circuit for use in an analog-to-digital (A/D) converter, and more particularly, to a current interpolation circuit for interpolating requisite reference voltages.
2. Description of the Prior Art
A conventional flash type A/D converter is one of the fastest structure which directly utilizes 2
n−
1 (n is the number of bit resolution) comparators to compare the input analog voltage with 2
n−
1 reference voltages and then generate n bits output digital code. The disadvantage of this structure is its large number of comparators needed, thus increasing power consumption and chip area.
A conventional folding type A/D converter is used to reduce the number of comparators. In this configuration, because all 2
n−
1 reference voltages are folded into 2
m
reference voltages (m<n) by a number of folding amplifiers, only 2
m
comparators are needed in this structure. In order to reduce the number of folding amplifiers required, the interpolation technique is commonly used in the folding structure. Many interpolation circuits are used to interpolate the output voltage by means of a number of series-connected impedance elements. However, this technique is not suitable for high speed A/D converter due to its need of converting the output current from the transconductance stage to the desirable voltage, which will disadvantageously produce an extra pole.
Current output from the folding amplifier is recently applied in several papers, for instance, IEEE JSSC, Jul. 1996, pp. 938-944 and IEEE JSSC, Sep. 1996, pp. 1248-1257, as shown in FIG.
2
and FIG.
3
. Unfortunately, the conventional interpolation circuits mentioned above require a great number of transistors to its implementation, which blocks the improvement for the modern integrated circuits. For the foregoing introduction, there is a need for an interpolation circuit used in an analog-to-digital (A/D) converter to substantially reduce transistor count and its power consumption.
SUMMARY OF THE INVENTION
The primary object of the present invention is to reduce the number of transistors needed in the current mode interpolation circuit, and, by the way, the bandwidth and the area of the current interpolation circuit are thus improved under available power.
In accordance with the present invention, the current interpolation circuit for use in an A/D converter includes two groups of current division circuits or current mirror circuits. One group of the current division circuits (or the current mirror circuits) generates some positive currents, and the other group of the current division circuits (or the current mirror circuits) generates some negative currents. One of the features of the present invention is the configuration of the input signals into a number of current comparators. Each current comparator has two input terminals, one terminal being coupled to receive one of the generated positive currents and the other terminal being coupled to receive one of the generated negative currents. The output of each current comparator is the differential current between these terminals, wherein the magnitude of the input positive current may not be the same as the magnitude of the input negative current. Then the differential current is converted to a voltage. The number of aforementioned positive currents is the same as the number of the negative currents, and the absolute value of each positive current is correspondingly the same as the absolute value of each negative current.
REFERENCES:
patent: 5384569 (1995-01-01), Komatsu
patent: 5594444 (1997-01-01), Yamada
patent: 5598161 (1997-01-01), Yamada
Jean-Pierre Peguy
United Microelectronics Corp.
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