Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2008-07-08
2008-07-08
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S212000
Reexamination Certificate
active
10930913
ABSTRACT:
To suppress variations of data currents dependent on a threshold voltage Vth of driving elements which form a current generation circuit. A current output section41ahas circuit systems in which a driving element DR and a switching element SW are connected in series, the number of the circuit systems corresponding to the number of the bits of input data. Each gate of the driving elements DR is commonly connected to a first node N1. The current output section41aoutputs data current Idata such that electrical currents flowing through each channel of the driving elements DR are merged in a state in which the voltage V1of the node N1of the node is set to a driving voltage. A gate voltage generation section41bsets the voltage V1of the node N1to an offset voltage corresponding to Vth by diode-connecting at least one of the driving elements DR. Also, the current output section41a sets the voltage V1to a driving voltage, in which the offset voltage is used as a reference, by varying a voltage Vref supplied to a terminal which is capacitively coupled to the node N1.
REFERENCES:
patent: 6501466 (2002-12-01), Yamagishi et al.
patent: 6765560 (2004-07-01), Ozawa
patent: 7109953 (2006-09-01), Abe et al.
patent: 7180479 (2007-02-01), Kimura
patent: 2003/0030602 (2003-02-01), Kasai
patent: 2005/0024352 (2005-02-01), Sano
patent: 2006/0119552 (2006-06-01), Yumoto
patent: A 2000-105574 (2000-04-01), None
patent: A 2000-122608 (2000-04-01), None
patent: A-2001-147659 (2001-05-01), None
patent: A-2002-514320 (2002-05-01), None
patent: A-2003-114645 (2003-04-01), None
patent: A 2003-195815 (2003-07-01), None
patent: A 2005-010683 (2005-01-01), None
patent: WO 98/48403 (1998-10-01), None
patent: WO 03/038795 (2003-05-01), None
Holton Steven
Oliff & Berridg,e PLC
Seiko Epson Corporation
Shalwala Bipin
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