Current controlled delay circuit

Details Current controlled delay circuit Current controlled delay circuit

2005-06-28

2005-06-28

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S288000, C327S280000, C327S270000

Reexamination Certificate

active

06911857

ABSTRACT:
A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The circuit includes a cross-coupled pair to switch the other of the two currents from one leg of the circuit to another leg of the circuit. The circuit may include a fixed or variable load.

REFERENCES:
patent: 5355097 (1994-10-01), Scott et al.
patent: 5994939 (1999-11-01), Johnson et al.
patent: 6043719 (2000-03-01), Lin et al.
patent: 6133773 (2000-10-01), Garlepp et al.
patent: 6396357 (2002-05-01), Sun et al.
John G. Maneatis, Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Patrik Larsson, A 2-1600-MHz CMOS Clock Recovery PLL with Low-V dd Capability, IEEE Journal of Solid-State Cuircuits, vol. 34, No. 12, Dec. 1999, pp. 1951-1960.

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