Pulse or digital communications – Receivers – Automatic frequency control
Reexamination Certificate
1999-06-17
2001-05-15
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Automatic frequency control
C375S324000, C375S343000, C375S361000, C327S017000, C327S074000
Reexamination Certificate
active
06233293
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to communication circuits, including continuous time integrated communication circuits, and is particularly directed to an improved on-chip, ‘carrier-tracking’ filter circuit, having a cut-off frequency that varies linearly with a control current supplied to a current-controlled oscillator, from which the carrier frequency to be tracked is derived.
BACKGROUND OF THE INVENTION
One of the requirements currently imposed (by the FCC) upon communication systems and networks is that they comply with very stringent spurious energy suppression standards. In today's digital communications environment, data signals (which have square rather than sinusoidal characteristics) are typically conditioned and modulated upon a higher carrier frequency (e.g., via emitter coupled logic circuitry (ECL)-based in-phase I and quadrature Q channels) where the data can be more readily transmitted.
Since the primary signal energy component of interest is located in the spectrum immediately surrounding the carrier center frequency, other spurious energy—typically the odd harmonics (multiples) of the original carrier frequency resulting from the modulation (multiplication or mixing) operation of such non-sinusoidal signals—must be removed, in order to avoid contaminating adjacent carrier channels that contain their own information energy components.
One way to remove such spurious energy is to apply the mixer output to a lowpass filter having a cutoff frequency that is slightly higher than the highest carrier frequency to be employed in a given communication system, such as a frequency-agile transceiver. Unfortunately, if the highest carrier frequency capable of being generated is close to the second or third harmonic of the lowest carrier frequency in the operating range of the system, the size (order) of the filter required to achieve sufficient unwanted energy suppression under all operating conditions is unacceptably large.
As a non-limiting example, in the case of conducting data communications over a television cable network, the required harmonic suppression filter may be an eight to twelve order filter. Such a large and complex filter is obviously impractical where cost and semiconductor silicon area are prime considerations in chip design. Moreover, such a large order filter has a higher group delay error, which can increase bit error rate.
Another technique is to add a filter pole to the carrier generator prior to the mixer. For a fixed carrier, adding a single pole is readily accomplished by simply adding a capacitor; however, in the case of a frequency-agile system, it is necessary to employ a plurality of capacitors, typically implemented as a programmable (controllably switched, binary weighted) capacitor array.
If the process employed to manufacture the integrated circuit architecture is a BiMOS process, MOSFET switches may be used to switch among the capacitors of the array. However, for a multiple channel system where there are a considerable number of potential carrier frequencies—requiring a separate capacitor for each carrier frequency, a binary-weighted capacitor array cannot be effectively employed, since the filter's cutoff frequency varies with the reciprocal of the value of the capacitor. As a consequence, if the cutoff frequency is to vary in a linear manner, the cutoff control capacitor must vary in a non-linear fashion, which not only again leads to an unacceptably large and complex filter, but the required switch array introduces parasitic poles, which are not readily compensated.
SUMMARY OF THE INVENTION
In accordance with the present invention, the shortcomings of the prior art filter proposals described above are successfully remedied by a post-mixer carrier frequency-tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The current-controlled MOSFET resistance-based filter mechanism has a transfer function which is established by an oscillator control current that controls the carrier frequency of interest.
The post-mixer carrier of the invention comprises a continuous time filter circuit, in particular a tunable g
m
/C filter, of the type commonly employed in high frequency telecommunication signal processing integrated circuit architectures. The fundamental building block of such a tunable g
m
/C filter is an integrator stage formed by combining a transconductance (g
m
) stage with an integrating capacitor. By cascading multiple integrator stages, a transconductance-C (g
m
-C) filter of any desired order may be realized, having a cutoff frequency f
o
that is effectively proportional to the ratio of g
m
to C.
The transfer functions of each of a tunable transconductance of the MOSFET-implemented resistance of a transconductance stage-capacitance filter and an associated transconductance tuning stage are effectively dependent upon the same oscillator control current that defines the output of a variable frequency synthesizer, which sources the carrier frequency of interest. In the modulation section of a transmitter device, this output carrier frequency and a baseband (data) signal are combined to produce a modulated carrier, which is then filtered by the carrier tracking filter.
The tunable transconductance of the transconductance stage-capacitance filter is referenced to a current mirror circuit, which replicates the control current for the variable synthesizer, and includes a differentially connected pair of matched bipolar transistors, each of which has an effective transconductance g
m
. The base electrodes of the differentially connected bipolar transistor pair are coupled to receive complementary input voltages that are centered around a common mode reference voltage level, and have their emitters coupled in circuit with respective controlled (emitter degeneration) MOSFET-implemented resistors. The gate electrodes of the MOSFET-implemented resistors are coupled in common to receive a control voltage that is derived from the transconductance tuning network, which operates the MOSFETs in the linear portion of their V
DS
−I
DS
characteristic.
The control voltage for the MOSFET-implemented resistors of the tunable transconductance stage is derived from a tuning network having a servo-loop connected, differential amplifier. A first input of the differential amplifier is coupled to a node between a fixed current source and a reference resistor, which is coupled in circuit with the emitter of a bipolar transistor. The fixed current source is preferably a PTAT reference current, so as to effectively eliminate temperature dependence. The current may be defined by the ratio of a voltage and a current-setting resistor comprised of the same resistor material as the reference resistor. A second input of the differential amplifier is coupled to a node between a mirrored current source, which supplies current having a magnitude that is a multiple (fractional or whole) of the oscillator control current and the source of a controlled MOSFET-implemented resistor that is coupled in circuit with the emitter of a bipolar transistor.
The bipolar transistors, to which the resistor inputs to the differential amplifier are coupled, are formed in the same integrated circuit chip as the tunable transconductance stage and are matched with its bipolar transistors. The controlled MOSFET-implemented resistor is configured identically to the MOSFET-implemented resistors of the tunable transconductance stage and has its gate electrode coupled to the output of the differential amplifier.
In operation, with a fixed current being supplied through the reference resistor to the first input of the differential amplifier and, with a mirrored, frequency synthesizer control current supplied through the MOSFET-implemented resistor to the second input of the differential amplifier, for a balanced servo loop condition, the two input voltages supplied to the respective inputs of the differential amplifier are equa
Godfrey Paul J.
Myers Brent A.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chin Stephen
Intersil Corporation
Liu Shuwang
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