Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-06-23
2010-02-09
Vo, Tuyet (Department: 2821)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S211000, C345S212000, C345S213000, C345S204000, C315S247000, C315S291000, C315S18500S, C315S312000
Reexamination Certificate
active
07659873
ABSTRACT:
A counter circuit increments a count value bit by bit in synchronization with a clock pulse received from an oscillating portion. A lower order decoder receives the count value output from the counter circuit, compares a bit or bits on a lower side with a set value1, and outputs an H-level only in a time period when the bit or bits match a bit pattern of set value1. Similarly, an upper order decoder compares a bit or bits on an upper side with a set value2, and outputs an H-level only in a time period when the bit or bits match the bit pattern of set value2. An AND circuit renders a transistor conductive in a time period when both lower and upper order decoders are outputting signals of the H-level.
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Nagao Kei
Nakao Shigeharu
Fish & Richardson P.C.
Rohm & Co., Ltd.
Vo Tuyet
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