Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-02-21
2002-05-07
Wong, Peter S. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S284000, C323S285000
Reexamination Certificate
active
06384584
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a current control circuit for detecting an overcurrent of a load and controlling a current flowing to the load.
2. Description of the Related Art
A conventional current control circuit will be described below with reference to
FIGS. 4 and 5
.
The current control circuit is constituted by a resistor R
11
having one end to which an input terminal IN for inputting an output of a power source is connected, a PMOS transistor M
11
having a source S connected to the other end of the resistor R
11
and a drain D connected to an output terminal OUT to be coupled to a load, a PNP transistor Q
11
having an emitter connected to the one end of the resistor R
11
, a base connected to the other end of the resistor R
11
and a collector connected to a gate G of the PMOS transistor M
11
, and an NPN transistor Q
12
having a base connected to a control terminal CTL, a collector connected to the source S and the gate G of the PMOS transistor Mll through resistors R
15
and R
16
respectively, and an emitter grounded.
With reference to
FIG. 3
, the operation of the current control circuit will be described below. A voltage drop in the resistor R
11
will be hereinafter referred to as V(R
11
) . When an overcurrent flows from the power source to the load, the V(R
11
) is increased so that the PNP transistor Q
11
is turned ON to raise a voltage on a point C. Consequently, an ON-state resistance of the PMOS transistor M
11
is increased so that a current flowing from the power source to the load is decreased. A value of a current flowing from the power source to the load is limited to V(R
1
)=0.7 V (volt) (hereinafter referred to as V) through a feedback group including the resistor R
11
, the PNP transistor Q
11
and the PMOS transistor M
11
. A drain current of the PMOS transistor M
11
obtained at this time is schematically shown in FIG.
4
.
A base-emitter voltage at which the PNP transistor Q
11
is turned ON is set to 0.7 V. For example, if V(R
1
) is set to be 0.1V, when a load current is in a normal state, an overcurrent flowing to the load is limited to seven times as great as that in the normal state.
A first problem is as follows. In a conventional current control circuit, a difference between a load current value in a normal state and a current value obtained when the overcurrent is limited is great and the limited overcurrent continuously flows to the load. Therefore, the PMOS transistor M
11
should have a great allowable loss. The allowable loss of a power transistor is mainly determined by performance for radiating an energy to be consumed by an element. Therefore, if the power transistor having a great allowable energy, a mounting space is increased so that an apparatus becomes large-sized.
A second problem is that the limited overcurrent continuously flows in the conventional current control circuit. Consequently, the load is damaged more greatly. The reason is that the power consumption in the load is increased because the current flows continuously.
SUMMARY OF THE INVENTION
It is an object of the present invention to detect an overcurrent of a load and to disconnect a current path to the load with few elements, thereby reducing a mounting space for a current control circuit and minimizing the damage of the load.
A first aspect of the present invention is a current control circuit comprising; a pair of input terminals for connecting a DC power source which outputs a prescribed output voltage, a pair of output terminals for connecting a load, a first resistor, one end of which is connected to one of the input terminals, a PNP transistor, for detecting an overcurrent flowing to the load, having an emitter connected to an one end of the first resistor and a base connected to the other end of the first resistor, a PMOS transistor, for controlling connection and disconnection between the DC power source and the load, having a source connected to the other end of the first resistor and a drain connected to one of the output terminals, a time constant circuit comprising a second resistor and a capacitor which are provided between a collector of the PNP transistor and the ground, and a hysteresis comparator, to which a voltage obtained by the time constant circuit is applied, for controlling a gate of the PMOS transistor.
A second aspect of the present invention is that an NPN transistor for controlling the PMOS transistor, a third resistor provided between a collector of the NPN transistor and the source of the PMOS transistor, a fourth resistor provided between a collector of the NPN transistor and the gate of the PMOS transistor, and a diode having an anode connected to an output of the hysteresis comparator and a cathode connected to the gate of the PMOS transistor, are provided.
As a first effect of the present invention, a switching transistor for turning ON/OFF the power path of the current control circuit can have a minimum allowable loss. Consequently, a mounting space of the current control circuit can be reduced.
As a second effect, the total amount of an energy of the overcurrent flowing to the load can be reduced considerably. Therefore, the load is less damaged.
The reason is as follows. When an overcurrent is detected, the current path is disconnected. For some period, therefore, a current temporarily flows to the load every constant time. A period for which the current path is maintained to be disconnected can be increased. Consequently, the power consumption of the load can be reduced.
REFERENCES:
patent: 5570004 (1996-10-01), Shibata
patent: 5977758 (1999-11-01), Noguchi et al.
patent: 3-60319 (1991-03-01), None
patent: 5-6366 (1993-01-01), None
patent: 6-187055 (1994-07-01), None
Laxton Gary L.
NEC Corporation
Wong Peter S.
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