Current cell driving circuit in digital-to-analog converter

Details Current cell driving circuit in digital-to-analog converter Current cell driving circuit in digital-to-analog converter

2001-12-27

2003-08-19

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S118000

Reexamination Certificate

active

06608578

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a digital-to-analog converter, and more particularly, to a current-steering digital-to-analog converter capable of minimizing glitch noises at an output terminal.
2. Description of the Prior Art
As a very large scale integration (VLSI) technology is rapidly growing according to Moore's law, it is possible to integrate analog and digital systems, which was realized on a conventional board, on a single chip. Therefore, the digital-to-analog converter (DAC), the interface block between the analog and digital systems, is considered as the key component completing the integrated system design.
DACs can be classified into a DAC for voice signal and a DAC for image signal based on the signal bandwidth. The DAC for voice signal processing has a sigma-delta structure for more than 16b resolution at low conversion rate. On the other hands, the DAC for image signal processing within the digital TV, HDTV, and medical equipment has a current-steering structure that can be implemented at high speed. A medium low-speed DAC having a R-2R ladder structure is applied to a portable measurement apparatus, an industry mechanical control apparatus, a digital control amplifier, and the like.
Usually, most high-speed and high-resolution DAC adopt a current-steering structure for its good linearity, operating speed and cost efficiency. There has recently been developed a current-steering DAC having a high static performance of over 12 bits resolution.
However, there is a problem that the dynamic performance of the current-steering DAC is abruptly degraded by glitch noise occurring at the output terminal, when the output signal frequency is increased to several dozens of MHz band.
Since the glitch noise is mainly caused by switch control signals, a current cell driving circuit generating the switch control signals is the critical block determining the dynamic performance of the current-steering DAC.
Therefore, examples for reducing the glitch noise include U.S. Pat. No. 5,463,394 issued on Oct. 31, 1995 (‘Current Switch for a High Speed DAC’), U.S. Pat. No. 6,295,012 issued on Aug. 25, 1999 (‘CMOS DAC with High Impedance Differential Current Drivers’), ‘A 12bit 200 MHz Low Glitch CMOS D/A Converter’ written in ‘CICC98’ by ‘A Van Bosch, et al.’ (June 1998) and ‘A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A Converter’ written in ‘IEEE, JSSC’ by ‘A Van Bosch, et al.’ (March 2001).
In order to reduce the glitch noise, the above prior arts employed methods of adjusting a cross point of differential control signals or reducing a transition time of the signals. As these methods, however, transit the control signals over the full range (from 0V to VDD or from VDD to OV) corresponding to the amount of the supply power voltage, there is a limit in reducing the glitch noise due to an influence of the control signals to the final output signal. Further, there was published a technology of reducing the amplitude of the control signals through voltage limiters. However, the conventional voltage limiters increase the transition time and make it difficult to be employed in high-speed applications.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems, and an object of the present invention is to provide a current cell driving circuit in a digital-to-analog converter (DAC) that can effectively limit the amplitude of the control signals and minimize the transition time, while not compromising the power consumption or the circuit area.
In order to accomplish the above object, a current cell driving circuit according to the present invention comprises a latch means for latching input signals depending on a clock signal to output first and second latch signals; and a voltage limiter means for limiting the first and second latch signals to a given level to output the first and second differential control signals.


REFERENCES:
patent: 5463394 (1995-10-01), Sun
patent: 6268816 (2001-07-01), Bult et al.
patent: 6295012 (2001-09-01), Greig
patent: 6414618 (2002-07-01), Bult et al.
IEEE 1998 Custom Integrated Circuits Conference, A 12 bit 200 MHz Low Glitch CMOS D/A Converter, 4 pages.
IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001, 10 pages.

Affiliated with

Also associated with

Rating

Current cell driving circuit in digital-to-analog converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Current cell driving circuit in digital-to-analog converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current cell driving circuit in digital-to-analog converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3085780