Current bit cell and switched current network formed of such cel

Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion

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341136, H03M 166

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active

061605077

ABSTRACT:
Current bit cell having a current source (P1), a transistor (P6) for detecting the presence of a digital signal bit (Bit) and a plurality of transistors (P2, P5, P7) for detecting at least one command signal (L, Lc) so as to command, on a first output (S1) of the cell, the appearance of a current delivered by the current source (P1) as a function of the digital signal (Bit) applied to the cell and of the at least one command signal (L, Lc), a transistor (P9) for detecting the presence of a bit (Bitz) complementary to the bit of the digital signal (Bit) and a plurality of transistors (P3, P4, P8) for detecting the complement (Lz, Lcz) of the at least one command signal (L, Lc), so as to command on a second output (S2) of the cell the appearance of a current delivered by the current source (P1) which is the complement of the current delivered on the first output (S1), the transistors for detecting the presence of bits and of the at least one command signal, the transistors for detecting the presence of complementary bits and of complementary command signals and the current source being embodied with the aid of field-effect transistors of the same type.

REFERENCES:
patent: 4393370 (1983-07-01), Hareyama
patent: 4490634 (1984-12-01), Hareyama
patent: 5105193 (1992-04-01), Vogt et al.
patent: 5148065 (1992-09-01), Krenik et al.
patent: 5331322 (1994-07-01), Cha et al.
patent: 5361233 (1994-11-01), Kotani
patent: 5369402 (1994-11-01), Kwon
patent: 5463394 (1995-10-01), Sun
IBM Technical Disclosure Bulletin, vol. 34, No. 10A, Mar. 1, 1992, New York, US, pp. 184-185, XP000302269 "Combined Sense Decoder and Amplifier" *p. 184, line 1-line 14; figure 1*.

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