Current biased phase locked loop

Details Current biased phase locked loop Current biased phase locked loop

2005-02-22

2005-02-22

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C327S156000, C327S157000, C327S159000

Reexamination Certificate

active

06859108

ABSTRACT:
A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal that is a selected multiple of an input reference signal. An oscillator control circuit increases and decreases the output frequency signal. A frequency detector detects a phase shift between the reference signal and the PLL output signal and produces an error signal. In response to the error signal, a fast lock circuit detects when the output frequency signal passes the selected multiple of the reference signal.

REFERENCES:
patent: 5986485 (1999-11-01), O'Sullivan
patent: 6411142 (2002-06-01), Abbasi et al.
U.S. patent application Ser. No. 09/730,954, Abbassi et al., filed Dec. 6, 2000.

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