Current-balanced logic circuit

Details Current-balanced logic circuit Current-balanced logic circuit

2006-03-28

2008-05-06

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S052000, C327S053000, C327S054000, C327S055000, C327S056000, C327S057000

Reexamination Certificate

active

07368955

ABSTRACT:
In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifiers are alternately activated by first and second differential clock signals, and when activated convert data received on differential input lines into logical values for storage in respective storage circuits. The storage circuits may be flip-flops, latches, keeper circuits, or other circuits for storing data.

REFERENCES:
patent: 4910713 (1990-03-01), Madden et al.
patent: 5124589 (1992-06-01), Shiomi et al.
patent: 5216295 (1993-06-01), Hoang
patent: 6014043 (2000-01-01), Nishida
patent: 6756823 (2004-06-01), Chen et al.
patent: 6867716 (2005-03-01), Zhang
patent: 6897697 (2005-05-01), Yin et al.
patent: 6937080 (2005-08-01), Hairapetian
patent: 7142029 (2006-11-01), Gregory
patent: 2004/0227544 (2004-11-01), Yin et al.
patent: 2005/0242843 (2005-11-01), Meltzer et al.
patent: 2005/0280460 (2005-12-01), Gregory
Moisiadis et al., A High-Performance Low-Power Static Differential Double Edge-Triggered Flip-Flop, pp. IV-802-IV805; IEEE 0-7803-6685-9/01.
Hossain et al., “Low Power Design Using Double Edge Triggered Flip-Flops”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, No. 2, Jun. 1994.
Strollo et al., “Low power double edge-triggered flip-flop using one latch”, Electronics Letters, Feb. 4, 1999; vol. 35, No. 3, pp. 187-188.
Allam et al., “Dynamic Current Mode Logic (DyCML): A New Low-Power High-Performance Logic Style”, IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001, pp. 550-558.
Lu et al., “A Novel CMOS Implementation of Double-Edge-Triggered Flip-Flops”, IEEE Journal of Solid-State Circuits, vol. 25, No. 4, Aug. 1990; pp. 1008-1010.
Mishra et al., “Design of high performance double edge-triggered flip-flops”, IEE Proc.-Circuits Devices Syst., vol. 147, No. 5, Oct. 2000, pp. 283-290.
Afghahi et al., “Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits”, IEEE Journal of Solid-State Circuits, vol. 26, No. 8, Aug. 1991, pp. 1168-1170.

Affiliated with

Also associated with

Rating

Current-balanced logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Current-balanced logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current-balanced logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3983548