Boots – shoes – and leggings
Patent
1986-02-06
1990-08-28
Williams, Jr., Archie E.
Boots, shoes, and leggings
3642328, 3642402, 3642434, 36424341, 3642526, 3642563, 3642564, 3642565, 3642592, G06F 934, G06F 1210, G06F 1316
Patent
active
049530739
ABSTRACT:
A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.
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Crudele Lester M.
Moussouris John P.
Przybylski Steven A.
Chan Emily Y.
MIPS Computer Systems, Inc.
Williams Jr. Archie E.
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