Cue delay circuit

Details Cue delay circuit Cue delay circuit

2005-06-28

2005-06-28

Miska, Vit W. (Department: 2841)

Horology: time measuring systems or devices

Combined with disparate device

C368S108000, C347S005000, C347S020000, C358S001150, C358S001160

Reexamination Certificate

active

06912179

ABSTRACT:
A cue delay circuit for an ink jet printing system includes a state machine with sequenced logic circuits that generate buffered control signals; a counter that counts one of the buffered control signals to form a read address; and an adder that combines the read address to the cue delay value to generate a write address. A comparator compares the cue delay value to the read address to determine if the read address is greater than the cue delay value. A multiplexer receives the read and write address and one of the buffered control signals and forms a multiplexer output. The system includes a gate circuit that receives the latched comparator output and the RAM output signal forming a gated cue signal; and a logic circuit that sends a signal to the printing system.

REFERENCES:
patent: 4045136 (1977-08-01), Watson et al.
patent: 4860219 (1989-08-01), Schulz et al.
patent: 5557304 (1996-09-01), Stortz
patent: 6109732 (2000-08-01), Wen
patent: 6559962 (2003-05-01), Fukunaga et al.
patent: 6803989 (2004-10-01), Silverbrook

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