Cubic memory array with diagonal select lines

Details Cubic memory array with diagonal select lines Cubic memory array with diagonal select lines

2002-07-23

2004-02-03

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000

Reexamination Certificate

active

06687147

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of electronic memory devices. More particularly, the present invention relates to a cubic memory array with select lines connected to multiple memory cells.
BACKGROUND OF THE INVENTION
Personal computers, servers, personal digital assistants, electronic games and other electrical devices use memory systems for storing data. An ever-increasing demand exists for larger and faster memory systems. Attributes of memory technologies include data access time (i.e. speed), cost, reliability, size (i.e. density), and electrical power dissipation.
Several memory technologies are widely used such as floppy drives, hard drives, compact disk (CD) drives and semiconductor memories. A semiconductor memory device is made up of a vast number of components called memory cells that each store a bit of data. Types of semiconductor memory include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), programmable read-only memory (PROM), one-time programmable (OTP), electrically erasable programmable read-only memory (EEPROM), and video random access memory (VRAM).
To increase the density of a semiconductor memory device, it is usually necessary to increase the density of the memory cells. However, as the density of memory cells increases within a given memory technology, there is a proportional increase in the amount of control elements needed to control and access the individual memory cells. In most cases each individual memory cell must have multiple electronic lines or connections that provide access to that memory cell and control the operations performed using that memory cell.
The area used for control electronics limits the area available for other digital circuits or system functionality. Additionally, increasing the amount of control elements may necessitate additional process layers so as to be able to fit a functioning memory cell and the required control elements in a given area. This adds to the time and money required to fabricate a memory array.
SUMMARY OF THE INVENTION
In one of many possible embodiments, the present invention provides a method of creating a memory circuit by (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.
Additional advantages and novel features of the invention will be set forth in the description which follows or may be learned by those skilled in the art through reading these materials or practicing the invention. The advantages of the invention may be achieved through the means recited in the attached claims.


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