Oscillators – Solid state active element oscillator – Transistors
Reexamination Certificate
2000-08-30
2001-10-16
Mis, David (Department: 2817)
Oscillators
Solid state active element oscillator
Transistors
C331S068000, C331S158000, C331S175000
Reexamination Certificate
active
06304151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a crystal oscillator in which a crystal blank and an IC (integrated circuit) chip are accommodated in a single vessel and a method of fabricating the same. In more particularly, the present invention relates to a crystal oscillator in which the IC chip is mounted to the vessel through a bump by using ultrasonic thermocompression bonding and a method of fabricating the same.
2. Description of the Related Art
A crystal oscillator is widely utilized as a device for providing a reference frequency and a reference time in various electronic apparatus including communication equipment. Recently, as is represented by portable equipment such as a portable telephone, the size of the apparatus becomes smaller and smaller. Thus, the crystal oscillator is also requested to be made small. The size requested for the crystal oscillator is, for example, 3 mm×5 mm for the bottom face thereof and 1 mm for the height itself. For this reason, when an IC chip included in the crystal oscillator is mounted on a package or the like, the manner of mounting is changed from a conventional wire bonding to a face down bonding (FDB) in which one major surface of the IC chip having terminal electrodes formed is brought face down and bonded to an opposing substrate. As an example of the face down bonding, there has been proposed a bonding method using ultrasonic thermocompression bonding employing a bump.
FIG. 1
is a diagram showing a cross-sectional view of an arrangement of a general crystal oscillator.
FIG. 2
is a magnified cross-sectional view of a part A of FIG.
1
.
A crystal oscillator is a device in which IC chip
2
and crystal blank
3
are accommodated in vessel main body
1
made of laminated ceramic and cover
4
is bonded onto vessel main body
1
so as to encapsulate therein IC chip
2
and crystal blank
3
. Cover
4
is made of ceramic and bonded to vessel main body
1
at the opening face thereof with glass
10
, for example. Vessel main body
1
is formed to have a concave portion. A pair of crystal terminals (not shown) are provided on the upper side wall of the concave portion serving as an open end of the concave portion. Also, a circuit pattern connected to the crystal terminal is provided on the bottom surface of the concave portion. Vessel main body
1
has outer electrodes
5
formed on the external bottom and side surfaces of vessel main body
1
so that outer electrodes
5
are connectable to a circuit pattern through a laminated layer face.
Crystal blank
3
has an excitation electrode (not shown) on each of the major surfaces. Also, crystal blank
3
has a leading electrode (not shown) which extends from the excitation electrode toward the both ends of one edge of crystal blank
3
. The leading electrode is electrically and mechanically connected to the above-described crystal terminal through conductive adhesive
9
, whereby crystal blank
3
can be held within the vessel main body
1
.
IC chip
2
is arranged as a flip chip in which electronic circuit components are integrated together with an oscillating circuit which uses crystal blank
3
. The flip chip is a so-called bare chip as it has been cut off from a semiconductor wafer such as a silicon wafer having undergone processes of semiconductor device fabrication. In the present case, IC chip
2
has a conventional arrangement suitable for achieving electrical connection by using wire bonding. That is, as shown in
FIG. 3
, in order to facilitate the process of wire bonding, a plurality of terminal electrodes (IC terminals)
6
are provided along a pair of sides opposing to each other on one major surface of IC chip
2
. An IC terminal for power supply and an IC terminal for ground are provided at corner portions of the major surface diagonally opposing to each other, in accordance with a standard.
Now, discussion is made on a case where IC chip
2
is mounted on a package or the like by means of wire bonding. When wire bonding is employed for mounting the IC chip, a thinned wire made of gold (Au) is employed as the bonding wire. One end of the wire is connected to each of IC terminals
6
. In order to decrease the electric resistance caused by the wire, particularly in the case of connection with the power supply IC terminal, unit terminals
6
a
and
6
b
each having the same size as that of an IC terminal for signal transmission, are connected to each other. Also, when an IC terminal for ground is formed on the IC chip, a pair of unit terminals
6
c
and
6
d
are connected to each other. Thus, wires can be connected in parallel, with the result that the resistance caused by the wire can be decreased to half. IC terminals include a terminal for signal output, a terminal for implementing a standby function and a terminal for connection to an external terminal or the like as well as a terminal for power supply and a terminal for ground. In the example shown in
FIG. 3
, a couple of unit terminals for ground and two IC terminals for signal transmission are arrayed along one side
10
a
of the chip. Further, a couple of unit terminals for power supply and five IC terminals for signal transmission are arrayed along the other side
10
b
of the chip.
While the above description was made on a case where IC chip
3
shown in
FIG. 3
is mounted by means of wire bonding, the following is a description made on a case where IC chip
2
can be mounted by means of face down bonding.
When the IC chip is mounted on the package or the like by means of face down bonding, bumps
7
each having a ball-shape made of gold (Au) or the like are formed on IC terminals
6
which are necessary to be electrically connected. In general, IC chip
2
is provided with a test terminal which is utilized when IC chip
2
is subjected to test before it is mounted. However, when IC chip
2
is subjected to test, the test terminal is directly connected to a test probe or the like. Further, when IC
2
is mounted on a package or the like, it is unnecessary for the test terminal to be electrically connected to a circuit on the package. Therefore, it is unnecessary for bump
7
to be provided on the test terminal. As for IC terminals for power supply, only one of unit terminals
6
a
and
6
b
has bump
7
formed thereon. Similarly, as for IC terminals for ground, only one of unit terminals
6
c
and
6
d
has bump
7
formed thereon. This is because the manner of mounting is not wire bonding and hence there is no resistance caused by a wire. Thus, it is expected that desired electrical connection will be accomplished by forming a bump on only one of the two unit terminals connected to each other. Each of bumps
7
is brought contact to terminal electrode (circuit electrode)
8
formed at the tip end of the circuit pattern configured on the bottom surface of concave portion
1
a
of vessel main body
1
. Thus, IC chip
2
is fixed to vessel main body
1
by means of face down bonding. In the example shown in
FIG. 3
, three bumps
7
in total are provided along side
10
a
of the major surface of the IC chip while five bumps
7
in total are provided along side
10
b
of the major surface of the IC chip.
Upon face down bonding of IC chip
2
, of major surfaces of IC chip
2
, a major surface on which a circuit, IC terminals
6
or the like are formed is brought into an opposing relationship with the bottom surface of concave portion
1
a
of vessel main body
1
. Then, IC chip
2
and vessel main body
1
are registered with each other so that bumps
7
and circuit terminals
8
of the circuit pattern are aligned with each other. When each of bumps
7
and corresponding one of circuit terminals
8
of the circuit pattern abut against each other, ultrasonic thermocompression, for example, is effected to make bumps
7
and circuit terminals
8
be fixed to each other. Ultrasonic thermocompression is effected in such a manner that a nozzle (not shown) is applied to the center of the upper surface of the IC chip and ultrasonic wave is supplied to the IC chip while press
Gong Xinglong
Makuta Toshikatsu
Negishi Susumu
Oda Seiji
Shibuya Tatsunobu
Mis David
Nihon Dempa Kogyo Co. Ltd.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
Crystal oscillator and method of fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Crystal oscillator and method of fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Crystal oscillator and method of fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2604045