Communications: electrical – Digital comparator systems
Patent
1974-03-27
1976-11-02
Urynowicz, Jr., Stanley M.
Communications: electrical
Digital comparator systems
340174SR, 340174AC, G11C 1114, G11C 1908
Patent
active
039900606
ABSTRACT:
The data stored in a coincident block access bubble domain memory with bit-organized chips is encrypted by skewing or permuting selected word bits by predetermined amounts. This is implemented by providing an additional current loop on some or all of the chips which overlies the major loop pattern and has nodes at the similar vector poles of the major loop. The proper energization of selected ones of these additional current loops, under the control of a security key, inhibits or suppresses the advance of the bubble domains in the corresponding major loops for a predetermined number of cycles of the in-plane propagating field, thus skewing the word bits in these chips with respect to the remaining word bits in the unsuppressed chips. Decryption is accomplished by further inhibiting the same major loops for the necessary number of cycles to restore word bit synchronization throughout the memory.
REFERENCES:
patent: 3508225 (1970-04-01), Smith
patent: 3613058 (1971-10-01), Bonyhard et al.
patent: 3618054 (1971-11-01), Bonyhard et al.
patent: 3701125 (1972-10-01), Chang
patent: 3701132 (1972-10-01), Bonyhard et al.
patent: 3737882 (1973-06-01), Furuoya
Lin Yeong S.
Liu Chao N.
Tang Donald T.
International Business Machines - Corporation
Urynowicz, Jr. Stanley M.
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