Crossbar switching matrix with broadcast buffering

Details Crossbar switching matrix with broadcast buffering Crossbar switching matrix with broadcast buffering

1999-05-19

2002-11-26

Luther, William A. (Department: 2664)

Multiplex communications

Data flow congestion prevention or control

Flow control of data transmission through a network

C370S360000, C370S395420, C710S040000, C710S309000

Reexamination Certificate

active

06487171

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to data communication switching systems and more particularly relates to a cross bar switching matrix having improved broadcast performance due to the utilization of broadcast buffering.
BACKGROUND OF THE INVENTION
Increasing reliance is being placed on data communication networks to carry increasing amounts of data. In a data communications network, data is transmitted end to end in groups of bits called packets, frames, cells, messages, etc. depending on the type of data communication network. For example, Ethernet networks transport frames, X.25 and TCP/IP networks transport packets and ATM networks transport cells. Regardless of what the data unit is called, each data unit is defined as part of the complete message that the higher level software application desires to send from a source to a destination. Alternatively, the application may wish to send the data unit to multiple destinations.
Currently, many switching systems utilize switching fabrics or matrixes that are designed to switch variable length packets of data. The variable length of packets in these switching systems, however, offer larger and less predictable switching delays as packet switching is more complex than fixed length packet switching.
Unicast, Broadcast and Multicast
The transmission of data to a single destination is termed unicast data while the transmission of data to all destinations is termed broadcast data. The transmission of data to a select number of destinations larger than one is termed multicast data. In an example switching system, each call connection within the switch has associated with it a routing tag or equivalent that functions to identify the destination for the packet.
For unicast connections, the routing information identifies a single destination for the packet. For broadcast connections, the routing information identifies the packet as a broadcast packet that is to be distributed to all output ports. For multicast connections, the routing information identifies several destinations for the packet.
A majority of data communication networks today attempt to not lose even a single bit of information in transmitting data from one point to another. In order to achieve such high levels of performance and low error rates, the network equipment is constructed with relatively large sized queues. The large queues are needed in order to handle the accumulation of packets without overflowing the queues. An overflow of a queue will result in packets being lost, i.e., dropped. Packets may be dropped at the source queue if the destination is full and thus cannot receive additional packets. In this case, the source queue fills up and at some point will overflow, with consequent packet loss.
A problem arises, however, with the transmission of broadcast packets through the switching matrix. In prior art switching systems, the switch must wait until the matrix tracks are cleared before a broadcast packet can be transmitted through the switch. All the output ports of the switch matrix must be free before the broadcast packet can be transmitted. This results in very large delays, which greatly reduces the efficiency and throughput of the switch matrix. The following example illustrates this problem.
A block diagram illustrating an example prior art crossbar switch matrix capable of handling unicast, broadcast and multicast traffic is shown in FIG.
1
. The switching system, generally referenced
10
, comprises a plurality of input/output (I/O) interface (I/F) cards
12
having a plurality of PHY interfaces, labeled
1
through M, and a plurality of outputs, labeled
1
through N. The system
10
further comprises an N×N crossbar switch matrix
14
having N input ports and N output ports. The N outputs of the I/F cards
12
are coupled to the N input ports of the switch matrix
14
. The N output ports of the switch matrix
14
are input back to the I/F cards
12
. A controller
16
functions to control the configuration of the switch matrix
14
at any particular point in time via one or more control lines
18
labeled CNTRL.
The crossbar switch is required to switch the entire set of input ports to the output ports in accordance with configuration information from the controller
16
. The controller
16
is responsible for providing the appropriate configuration information to the crossbar switch matrix
14
at the correct time. The crossbar switch
14
performs the switching operation in accordance with the switching information provided by the controller. In the event of a broadcast packet to be transmitted from any of the I/F cards, the configuration controller
16
provides the appropriate switching commands which cause the broadcast packet to be transmitted to all the output ports. This is achieved by the issuance of the suitable configuration commands to each I/F card. All I/F cards (except the one transmitting the broadcast packet) and all the input ports will be in the idle state for a broadcast transmission to occur.
A block diagram illustrating the I/O interface (I/F) card of the prior art switch in more detail is shown in FIG.
2
. The I/O card
20
comprises a PHY interface
24
to/from a physical connection
22
. The I/O card also comprises a controller/packet processor
26
, memory
27
, output queues
28
, input queue
30
, host interface
25
and backplane interface
29
.
The I/O card comprises N output queues
28
, labeled Q
1
through Q
N
, one queue corresponding to each output port of the switch matrix. An additional broadcast queue, labeled Q
BC
, is also included for buffering packets to be broadcast to all output ports. Note that the queues may optionally be implemented using the memory
27
. The queues interface to the switch matrix via a backplane interface
29
.
The PHY interface
24
is coupled to a controller/packet processor
26
that functions to receive packets and route them to the appropriate output queue. Note that the PHY interface
24
may be adapted to handle electrical or optical signals, e.g., OC-3, OC-12, SONET, 1000BaseT, etc.
In operation, the format of the received signal is converted to packets and input to the packet processor
26
. The packet processor
26
functions to process the data destined to the ingress of the switching matrix and to process the data output from the egress of the switching matrix. The packet processor, in accordance with the connection information, determines a destination output port for data received over the PHY I/O channel. For unicast transmission, the packet processor places the packet in one of N queues
28
corresponding to one of N output ports. For broadcast connections, the packet is placed in the broadcast queue Q
BC
for broadcast to all output ports simultaneously.
When packets are output of the switch matrix, they return to the I/F card corresponding to the output port. A backplane interface
29
interfaces the input and output queues to the switch matrix. Packets destined to an output queue on a particular I/F card, are input to the output queue Q
o
30
via the backplane interface
29
. The packet is then input to the packet processor
26
and output to the PHY via the PHY interface
24
.
Note that a unicast queue is a physical queue that accumulates packets designated to be transmitted to a single destination queue and is associated with a point to point connection. A broadcast queue is a physical queue that accumulates packets designated to be transmitted to all destination queues
A disadvantage of this prior art switching architecture is that the transmission of broadcast packets occurs only when all the input ports are in the idle state, i.e., they are not in the middle of transmitting a packet of data. In addition, during the transmission of a broadcast packet, all the I/F cards, except the one transmitting the broadcast packet, are also in the idle state. Since the switch is constructed to transmit variable length packets, the waiting time until all the I/F cards and input ports are in the idle state, i.e., have completed their current

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