Crossbar interface for data communication network

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364DIG1, 3642295, 36423951, 3642419, 3642448, 3642841, G06F 1314

Patent

active

052610594

ABSTRACT:
An interface between a host computer and a crossbar switch is provided which employs data buffering using multiple-port RAM devices. The receive and transmit data is clocked into or out of separate serial ports of the RAM, and at the same time a local processor can access the RAM by a random access port, asynchronous to the serial ports, to execute the protocol. The order of storing bursts of data in the multiple-port RAM is defined by a free buffer manager which keeps account of which locations are free. The addresses of these locations are moved to a received list after being used for incoming packets. After the protocol processor has finished with its tasks, these addresses, referred to as burst data descriptors, are moved to a transmit list to await loading of burst data back to the serial registers for clocking out, then when transmitted the descriptors are again entered into the free buffer manager.

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"High-Performance Parallel Interface" Protocol Specification, American National Standard for Information Systems, Nov. 1, '89, pp. 1-30.

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