Cross under metal wiring structure for self-scanning...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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Details

C257S091000, C257S743000, C257S745000

Reexamination Certificate

active

06507057

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a self-scanning light-emitting device, in particular to a cross under metal wiring structure for a self-scanning light-emitting device.
BACKGROUND ART
A light-emitting device in which a plurality of light-emitting elements are arrayed on the same substrate is utilized as a light source of a printer, in combination with a driver circuit. The inventor of the present invention has interest in a three-terminal light-emitting thyristor having an pnpn-structure as an element of the light-emitting device, and has already filed several patent applications (see Japanese Patent Publication Nos. 1-238962, 2-14584, 2-92650, and 2-92651.) These publications have disclosed that a self-scanning function for light-emitting elements may be implemented, and further have disclosed that such self-scanning light-emitting device has a simple and compact structure for a light source of a printer, and has smaller arraying pitch of thyristors.
The inventor has further provided a self-scanning light-emitting device having such structure that an array of light-emitting thyristors having transfer function is separated from an array of light-emitting thyristors having writable function (see Japanese Patent Publication No. 2-263668.)
Referring to
FIG. 1
, there is shown an equivalent circuit diagram of a fundamental structure of this self-scanning light-emitting device. According to this structure, the device comprises an array of transfer elements T
1
, T
2
, T
3
, . . . and an array of writable light-emitting elements L
1
, L
2
, L
3
, . . . , these elements consisting of three-terminal light-emitting thyristors. The structure of the portion of an array of transfer elements includes diode D
1
, D
2
, D
3
, . . . as means for electrically connecting the gate electrodes of the neighboring transfer elements to each other. V
GK
is a power supply (normally 5 volts), and is connected to all of the gate electrodes G
1
, G
2
, G
3
, . . . of the transfer elements via a load resistor R
L
, respectively. Respective gate electrodes G
1
, G
2
, G
3
, . . . are correspondingly connected to the gate electrodes of the writable light-emitting elements L
1
, L
2
, L
3
, . . . A start pulse &phgr;
s
is applied to the gate electrode of the transfer element T
1
, transfer clock pulses &phgr;
1
and &phgr;
2
are alternately applied to all of the anode electrodes of the transfer elements, and a write signal &phgr;
I
is applied to all of the anode electrodes of the light-emitting elements.
In
FIG. 4
, R
1
, R
2
and R
I
designate current limiting resistors, respectively.
The operation of this self-scanning light-emitting device will now be described briefly. Assume that as the transfer clock &phgr;
1
is driven to a high level, the transfer element T
2
is turned on. At this time, the voltage of the gate electrode G
2
is dropped to a level near zero volts from 5 volts. The effect of this voltage drop is transferred to the gate electrode G
3
via the diode D
2
to cause the voltage of the gate electrode G
3
to set about 1 volt which is a forward rise voltage (equal to the diffusion potential) of the diode D
2
. On the other hand, the diode D
1
is reverse-biased so that the potential is not conducted to the gate G
1
, then the potential of the gate electrode G
1
, remaining at 5 volts. The turn on voltage of the light-emitting thyristor is approximated to a gate electrode potential+a diffusion potential of pn-junction (about 1 volt.) Therefore, if a high level of a next transfer clock pulse &phgr;
2
is set to the voltage larger than about 2 volts (which is required to turn-on the transfer element T
3
) and smaller than about 4 volts (which is required to turn on the transfer element T
5
), then only the transfer element T
3
is turned on and other transfer elements remain off-state, respectively. As a result of which, on-state is transferred from T
2
to T
3
. In this manner, on-state of transfer elements are sequentially transferred by means of two-phase clock pulses.
The start pulse &phgr;
s
works for starting the transfer operation described above. When the start pulse &phgr;
s
is driven to a low level (about 0 volt) and the transfer clock pulse &phgr;
2
is driven to a high level (about 2-4 volts) at the same time, the transfer element T
1
is turned on. Just after that, the start pulse &phgr;
s
is returned to a high level. Assuming that the transfer element T
2
is in the on-state, the voltage of the gate electrode G
2
is lowered to almost zero volt. Consequently, if the voltage of the write signal &phgr;
I
is higher than the diffusion potential (about 1 volt) of the pn-junction, the light-emitting element L
2
may be turned into an on-state (a light-emitting state).
On the other hand, the voltage of the gate electrode G
1
is about 5 volts, and the voltage of the gate electrode G
3
is about 1 volt. Consequently, the write voltage of the light-emitting element L
1
is about 6 volts, and the write voltage of the light-emitting element L
3
is about 2 volts. It is appreciated from this that the voltage of the write signal &phgr;
I
which can write into only the light-emitting element L
2
is in a range of about 1-2 volts. When the light-emitting element L
2
is turned on, that is, in the light-emitting state, the amount of light thereof is determined by the amount of current of the write signal &phgr;
I
. Accordingly, the light-emitting elements may emit the light at any desired amount of light. In order to transfer on-state to the next element, it is necessary to first turn off the element in on-state by temporarily dropping the voltage of the write signal &phgr;
I
down to zero volts.
The self-scanning light-emitting device described above may be fabricated by arraying a plurality of chips each thereof being 600 dpi (dot per inch)/128 light-emitting points and having 5.4 mm length. These chips are fabricated on a wafer and obtained by dicing them.
An example of an element arrangement in a chip for the self-scanning light-emitting device is schematically shown in FIG.
2
. In the figure, L
1
-L
128
designate light-emitting elements, T
1
-T
128
transfer elements,
40
and
50
bonding pads for clock pulses &phgr;
1
and &phgr;
2
,
60
a bonding pad for a start pulse &phgr;
s
,
70
a bonding pad for a write signal &phgr;
I
,
80
a bonding pad for a power supply V
GK
, and
90
a bonding pad for an output D
out
, respectively. Reference numeral
100
denotes the outer line of the chip.
In the element arrangement shown in
FIG. 2
, a number of metal wirings are required for connecting the light-emitting elements and transfer element in an array fashion. In particular, four metal wirings for &phgr;
1
, &phgr;
2
, V
GK
, and diode connection make a detour around the bonding pads
40
,
50
and
70
provided at a center of the chip.
FIG. 3
shows the metal wirings around the bonding pad
40
for &phgr;
1
. In the figure, an example is shown wherein a current limiting resistor R
1
(see
FIG. 1
) is built in the chip. Reference numerals
2
,
3
,
4
and
5
designate &phgr;
1
wiring, &phgr;
2
wiring, V
GK
wiring, and diode connection wiring, respectively. Apparent from the figure, these wirings are formed so as to make a detour around the bonding pad
40
.
Such detour of wiring causes the problem in that the size of a chip is enlarged. In order to resolve this problem, there is an approach such that the wirings are formed in a two-layer structure as shown in FIG.
4
. That is, the V
GK
wiring
4
and diode connection wiring
5
are formed under the &phgr;
1
wiring
2
and &phgr;
2
wiring
3
. In
FIG. 4
, the portion where the wiring
4
and
5
are crossed with the wirings
2
and
3
is shown as a cross under wiring portion
6
circled by a dotted line
6
. Also, at the portion where the &phgr;
1
wiring
2
and &phgr;
2
wiring are crossed each other, the &phgr;
2
wiring
3
is formed under the &phgr;
1
wiring
2
. In
FIG. 4
, the portion where the &phgr;
1
wiring
2
and &phgr;
2
wiring
3
are crossed each other is denoted as a cross under

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