Wave transmission lines and networks – Plural channel systems
Reexamination Certificate
1999-11-30
2003-12-09
Le, Dinh T. (Department: 2816)
Wave transmission lines and networks
Plural channel systems
C333S012000, C327S551000
Reexamination Certificate
active
06661303
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of communication systems and more particularly to a method and system for suppressing cross talk in a bidirectional bus.
2. History of Related Art
The various components in an electronic system typically communicate with each other using a multitude of conductive pathways or interconnects to provide communications or connectivity between the components. Frequently, the interconnects are organized into logical groups or busses which communicate related signals from one device to another. Typically, the busses are physically organized as a set of closely spaced, parallel interconnects.
The ongoing development of high-speed digital systems places increasing importance on signal integrity issues. As device speeds and integration levels increase with advances with semiconductor fabrication technology, multi-gigahertz communication bandwidths are expected at all levels of the interconnection hierarchy. Cross talk voltages in closely coupled communication busses are a major constraint in the design of high density busses whether on chip, on multi-chip modules, or on printed wiring boards. Delay can be reduced by increasing the characteristic impedance of the interconnects. Unfortunately, the ability to increase the characteristic impedance by, for example, increasing the thickness of an underlying dielectric layer is limited by other processing considerations. At some point, the ability to lower delay by manipulating the physical dimensions of the interconnect is offset by considerations of circuit density, cross talk, and bandwidth. Therefore, it would be advantageous to design an interconnect bus with inherent cross talk suppression. Such an approach is particularly suitable for “standard” interconnect circuit blocks such as processor-to-memory communication busses. It would be further desirable if the implemented communication bus did not significantly increase the number of I/Os, line pitch, or other important physical characteristics of the communication bus.
SUMMARY OF THE INVENTION
A bidirectional bus and data processing system suitable for suppressing cross talk noise are disclosed. The bidirectional bus includes a first interconnect line driven by a pair of drivers, a first pair of impedance elements connected between the first line and a second line of the bus, and a second pair of impedance elements connected between the first line and a third line of the bus. In one embodiment, each of the first pair of impedance elements comprises a NMOS/PMOS transistor pair where the drains of the transistor pair are connected to the second line and the sources of the transistor pair are connected to the first line. In one embodiment, the gate terminal of the NMOS transistor, in the transistor pair is connected to VDD and the gate terminal of the PMOS transistor is connected to ground. In one embodiment, the capacitive coupling per unit length between the first line and the second line is approximately equal to k and the impedance of the first pair of impedance elements is approximately equal to (&ugr;k)
−1
, where &ugr; is the speed of light through a dielectric in which the first and second lines are embedded. In one embodiment, the impedance of the first driver is approximately equal to (&ugr;c
0
)
−1
, where c
0
is the self-capacitance of the first line. The driver may comprise a CMOS inverter, where the input of the inverter is driven by a first input signal and the output of the inverter is connected to the first line. In one embodiment, the first driver is configured to draw current from the second and third lines when the first driver drives the first line. In one embodiment, the current drawn by the driver from the second and third lines offsets the current induced in the second and third lines when the first line is driven by the first driver. In one embodiment, the current in the first line is I when the first line is driven by the first driver and the current drawn from the second and third lines is J, where J/I is approximately equal to k/c where c is approximately c
0
+2k. The current source may comprise a current sourcing transistor with its drain coupled to the second line, its source connected to a supply terminal, and its gate connected to the output of a reference voltage generator. In one embodiment, the current source may further include a pass transistor connected between the drain terminal of the current sourcing transistor and the second line, wherein the pass transistor is driven by the inverse of an input signal to the first driver circuit. The reference voltage generator may include an n-channel device with its source connected to the supply terminal and its gate and drain connected to a reference voltage node, an NMOS/PMOS transistor pair with its source terminals connected to the reference voltage node, its drain terminals connected to a first node, the gate of the PMOS transistor connected to the supply terminal, and the gate of the NMOS transistor connected to V
DD
, and a pair of PMOS devices between VDD and the first node, where the gates of the PMOS devices are connected to their respective drains.
REFERENCES:
patent: 5027088 (1991-06-01), Shimuzu et al.
patent: 6008705 (1999-12-01), Goshal
Lally Joseph P.
Le Dinh T.
Salys Casimer K.
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