Static information storage and retrieval – Floating gate
Patent
1994-04-05
1995-11-14
Yoo, Do Hyun
Static information storage and retrieval
Floating gate
365 63, 365218, 257314, 257316, G11C 1140
Patent
active
054673089
ABSTRACT:
A cross-point EEPROM memory array includes a semiconductor substrate (10) having first and second bit-lines (32, 34) spaced apart by a channel region (36). A control gate electrode (24) is formed by a portion of a control gate line, which overlies a first portion of the channel region (36) and is separated therefrom by an ONO layer (17). A select gate electrode (40) is formed by a portion of a select gate line disposed on the substrate (10) perpendicular to the control gate line. Individual cells in the array are programmed by injecting electrons using source-side injection into trapping sites (19) in the silicon nitride layer (14) of the ONO layer (17). The cells in the array are erased by electron tunneling through the top silicon dioxide layer (16) of the ONO layer (17), and are dissipated in the control gate electrode (24). Improved operating performance is obtained, in part, by fabricating the first silicon dioxide layer (12) of the ONO layer (17) to a greater thickness than the top silicon dioxide layer (16) of the ONO layer (17).
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Chang Ko-Min
Chang Kuo-Tung
Dockrey Jasper W.
Motorola Inc.
Yoo Do Hyun
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