Cross point array memory device

Details Cross point array memory device Cross point array memory device

1990-05-03

1991-07-23

Moffitt, James W.

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

365208, G11C 506

Patent

active

050349201

ABSTRACT:
A memory array layout using complementary bitlines connected to a single sense amplifier. Extending from the sense amplifier, bitlines which are unconnected are extended to the middle of the array. One complementary bitline is then connected to a series of memory cells extending away from the sense amplifier. The other complementary bitline loops back and is connected to a set of memory cells extending back toward the sense amplifier. The first bitline section extending from the sense amplifier may be advantageously formed in a metal layer above the substrate thereby occupying no space in the substrate itself. All noise generated on the first sections of the bitlines will be canceled by the complementary parallel structure of the bitlines. Because the second sections of the bitlines are laterally separated, a wordline passing across each of the second sections addresses a singel memory cell. Therefore an optimally compact cross-point memory array may be fabricated. Using the described techniques an optimally compact array having an improved signal to noise characteristic may be fabricated.

REFERENCES:
patent: 4581720 (1986-04-01), Takemae et al.
patent: 4701884 (1987-10-01), Aoki et al.

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