Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2000-01-13
2004-11-09
Holloway, III, Edwin C. (Department: 2635)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C340S002210
Reexamination Certificate
active
06816486
ABSTRACT:
TECHNICAL FIELD
The present invention relates, in general, to interconnection topologies between circuit boards in a chassis, and more specifically, to an interconnection topology for large arrays of switching modules requiring high speed.
BACKGROUND OF THE INVENTION
Three stage switches are known in the art. As the name implies, three stage switches typically have three stages, namely, an input stage, a middle stage and an output stage.
The interconnection topology for arrays, of this type includes is one signal path from each of a number of input subswitches connected to each of a number of middle subswitches which in turn have one path connecting them to a number of output subswitches. An example of this is the INRANGE Technologies Corp. 2700 matrix switch. The 2700 switch includes 128 input subswitches with 32 input ports per subswitch. The 2700 switch provides one signal path from each of these input subswitches to 64 middle subswitches. One output from each of these middle subswitches may be connected to each of 128 output subswitches. Each output subswitch includes 32 outputs.
Referring to
FIG. 1
, there is shown a conventional three stage matrix switch, generally designated as
10
. The input stage includes 128 input subswitches, designated as
12
a
-
12
n
. Each input subswitch includes a 32×64 input submatrix having 32 input receivers and 64 single ended output drivers. Although not shown, each input receiver may be connected to each of the 64 output drivers.
As an example of input receivers connected to output drivers, an 8×16 submatrix switch
100
is shown in FIG.
8
. As shown, switch
100
includes 8 input receivers
102
(on the horizontal lines) and 16 output drivers
104
(on the vertical lines). At the intersection of each horizontal and vertical line, a crosspoint switch is shown as indicated by a diagonal line. If the switch at any intersection (crosspoint) is off, that input is not connected to that output. If the switch is on, that input is connected to that output. In the example shown in
FIG. 8
, In-
5
is connected to Out-
9
by crosspoint switch
106
being on. In this manner, it is possible for any input to be connected to any output or for any input to be connected to multiple outputs.
Referring again to
FIG. 1
, the middle stage includes 64 middle subswitches, designated as
14
a
-
14
m
. Each middle subswitch includes a 128×128 middle submatrix having 128 input receivers and 128 output drivers. Although not shown, each input receiver of middle submatrix
14
a
may be connected to each of the 128 output drivers.
Still referring to
FIG. 1
, the output stage includes 128 output subswitches, designated as
16
a
-
16
n
. Each output subswitch includes a 64×32 output submatrix having 64 input receivers and 32 output drivers. Similar to the other stages, each input receiver of output submatrix
16
a
may be connected to each of the 32 output drivers.
Thus, matrix switch
10
includes 4096 (32×128=4096) line receivers, which are respectively connected to 4096 external input ports, designated as
18
. Matrix switch
10
also includes 4096 line drivers at the output stage, which are respectively connected to 4096 external output ports, designated as
20
. Connections between the output drivers of the first stage
12
a
-
12
n
and the input receivers of the middle stage
14
a
-
14
m
are made by way of a plurality of wires
22
, which reside in backplanes of the chassis (not shown). Similarly, connections between the output drivers of the middle stage and the input receivers of the third stage
16
a
-
16
n
are made by way of a plurality of wires
24
, which also reside in the chassis backplanes (not shown).
Matrix switch
10
is physically arranged into a plurality of modules or circuit boards. Each module or circuit board includes an input cross-point array of one 32×64 input submatrix
12
a
and an output cross-point array of one 64×32 output submatrix
16
a
. These modules are hereinafter referred to as input/output modules. Another type of module or circuit board is included in matrix switch
10
, hereinafter referred to as middle matrix modules. Each middle matrix module includes one 128×128 middle submatrix
14
a
. Thus, matrix switch
10
, as shown in
FIG. 1
, includes 4096 input ports and 4096 output ports, 128 input/output modules and
64
middle matrix modules.
The modules of matrix switch
10
are arranged physically in eight chassis. One such chassis is shown in FIG.
2
and is generally designated as
30
. As shown,
24
circuit boards are plugged into chassis
30
. These boards include 16 input/output modules (designated as I/OM
1
-I/OM
16
) and 8 middle matrix modules (designated as MMM
1
-MMM
8
). The modules plug into the chassis from the front and are horizontally oriented, as shown. A sixteen layer backplane, designated as
32
, is required to interconnect the modules in the chassis and to connect the modules to connectors
34
on the chassis. Connectors
34
provide connections to other chassis in matrix switch
10
. For example, connectors
34
permit sending 3584 single-ended signals to other chassis in matrix switch
10
.
Although matrix switches of the type shown in
FIGS. 1 and 2
have been adequate, the ever increasing speed of communication in networks has resulted in exceeding the speed capabilities of many existing matrix switches. One obstacle to producing faster switches is the need for balanced signaling between modules. Because of the need for maintaining matched impedances and minimal signal length differentials within signal pairs, there is the need to double the number of signals interconnecting the modules. Doubling the number of signals on each backplane may necessitate increasing the number of backplane layers from 16 to 32. The number of signals interconnecting a chassis may also need to be doubled. Also, the distance a signal travels tends to lower the overall speed of the switch. As a result, a need still exists to develop a matrix switch that may be used in high speed applications requiring balanced differential signal pairs. A need also exists to develop a high speed matrix switch without increasing the number of backplane layers in the chassis.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides a chassis for holding modules including a set of first modules oriented horizontally in the chassis and a set of second modules oriented vertically in the chassis. A midplane is oriented orthogonally to the sets of first and second modules. Connector pins extend from a first side of the midplane through to the second side of the midplane. Each of the first modules has a first connector for mating with the connector pins extending from the first side, and each of the second modules has a second connector for mating with the connector pins extending from the second side. Each of the first modules includes first and third stages of switching arrays and each of the second modules includes a second stage of switching arrays, wherein the first, second and third stages of switching arrays are sequentially connected in series. A signal is routed from the first stage into the second stage by way of at least one pin of the connector pins on the midplane, and then sequentially routed from the second stage to the third stage by way of at least another pin of the connector pins on the midplane. The first and second connectors are female connectors for respectively mating with the connector pins extending from the first and second sides of the midplane. The midplane includes power and ground signals.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 4393381 (1983-07-01), Seiden
patent: 4472765 (1984-09-01), Hughes
patent: 4703394 (1987-10-01), Petit
patent: 4876630 (1989-10-01), Dara
patent: 4878215 (1989-10-01), Rogers
patent: 5640387 (1997-06-01), Takahashi
patent: 5675580 (199
Beck & Tysuer PLLC
Holloway III Edwin C.
Inrange Technologies Corporation
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