Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – With means to prevent edge breakdown
Reexamination Certificate
2001-04-13
2002-09-24
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
With means to prevent edge breakdown
C257S170000, C257S409000, C257S452000, C257S605000, C257S774000
Reexamination Certificate
active
06455910
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application Ser. No. 90108503, filed on Apr. 10, 2001.
BACKGROUND OF THE INVENTION
1. Filed of Invention
The present invention relates generally to semiconductor and more specifically to a cross guard-ring structure.
2. Description of Related Art
Integrated circuits are manufactured as assemblies of the various devices, such as transistors that make up a chip and many chips are included on a single wafer. In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together and packaged onto the suitable circuit board to perform the desired circuit functions. However one problem is the moisture induced chip cracking often occurs during the packaging process. During the packaging process, for example during the reflow soldering process, the chip is exposed to a higher temperature of about 215-260° C. As a result the moisture from the ambient will concentrate on the boundary surface between the chip pad and molding resin and flashes into steam under the high temperature. Because the adhesion there is usually poor and also because the plastic section over and under the chip/lead frame surfaces are very thin, the steam pressure is sufficient to rupture the thinner packages. As a result, cracking of the chip occurs. Consequently, moisture will penetrate into the chip and if the internal circuitry of the chip are unprotected from moisture, the moisture would corrode the wiring and interconnect structures. As a result the resistance of the wiring structure increases. Because the resistance is increased, the RC delay time is therefore increased, therefore the operating speed is reduced. Eventually the functionality of the device ceases.
Presently in IC manufacturing, the wiring in chip level interconnects and the device itself are normally protected from moisture by various layers of inorganic dielectrics consisting of oxides or nitrides such as silicon nitride and/or silicon oxide. In addition to being effective as moisture barrier layers, inorganic dielectrics are also excellent barriers against the migration of ions which can be present as contaminants or in processing fluids such as etching solutions. Such ions may corrode the metal wiring as well as migrate to the semiconductor itself wherein the migrating ions may form fast moving silicides which essentially destroy the semiconductor device.
Recently, organic dielectric materials such as polyimides, polybenzocyclobutanes (BCBs) and poly(arylene ethers) have drawn considerable interest for their low dielectric constant properties thus reduce signal delays. But one problem is that they are hygroscopic so they tend to be permeable to moisture and other contaminants. This permeability problem is particularly detrimental to Cu wiring which can oxidize in the presence of moisture. In addition, ions such as iron, copper, sodium, and/or potassium ions among others can corrode the Cu wiring. Furthermore, ions such as iron and copper can potentially migrate to the semiconductor where they form fast moving suicides which may destroy the device. One scheme is to use the inorganic dielectric materials such as silicon oxide and silicon nitride material as barrier layers in order to protect the organic dielectric material from moisture and other contaminants. However one problem with the inorganic and organic dielectric materials is that they are very fragile. The fragileness is the main problem because of the thermal stress caused due to the packaging process as described above, can easily crack the said dielectric layers and thus chip crack occurs. As a result, moisture and other contaminants can easily penetrate through the crack lines into the chip and may destroy the device.
In view of the drawbacks mentioned hereinabove it is therefore highly desirable to provide a protective structure which can effectively prevent the chip crack so that moisture and/or ions can be effectively prevented from penetrating to the Cu wiring of such IC interconnect structures. Thus the reliability of the device can be enhanced.
SUMMARY OF THE INVENTION
The present invention provides a cross guard ring structure which serves to protect the chip from cracking so that penetration of moisture into the chip can be effectively prevented. Therefore the reliability of the device can be enhanced.
The present invention provides a cross guard ring structure along the edge of a semiconductor chip structure so that the chip structure is protected from chip crack during the packaging process.
The present invention provides a cross guard ring structure so that the above objectives and other objects are met.
These and other objects and advantages are achieved in the present invention by placing guard rings along the edge of an IC chip so that the chip can be effectively protected from cracking due to thermal stress which is induced due to the packaging process.
Specifically, the present invention provides a cross guard ring structure. A first guard ring, a second guard ring and a third guard ring are formed and concentrically positioned along the edge of a semiconductor chip, as shown in FIG.
1
. Each guard ring comprises several rectangle shaped copper vias which are positioned along the edge of the chip structure, wherein each copper via is separated from an adjacent copper via by a gap. Further, each copper via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with copper vias of the first guard ring which are separated by the said gap as shown in FIG.
2
. Similarly the third guard ring is position with respect to the second guard ring. The first guard ring, the second guard ring and the third guard ring are separated from each other by a space.
It is to be understood by those skilled in the art that because the cross guard ring structure is positioned along the edge of a semiconductor chip, therefore chip crack due to thermal stress can be effectively prevented.
It is to be further understood by those skilled in the art that because chip crack can be effectively prevented by positioning a cross guard ring structure along the edge of a semiconductor chip, therefore moisture and other contaminants cannot penetrate into the chip which would otherwise corrode the wiring and interconnect structure present therein and destroy the functionality of the semiconductor chip. Thus the reliability of the semiconductor device can be substantially enhanced.
It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the present invention.
REFERENCES:
patent: 5266831 (1993-11-01), Phipps et al.
patent: 5274263 (1993-12-01), Wadsworth
patent: 5838050 (1998-11-01), Ker et al.
patent: 6160303 (2000-12-01), Fattaruso
patent: 1-227473 (1989-09-01), None
J. C. Patents
Lee Eddie
United Microelectronic Corp.
Warren Matthew E.
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