Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Shift direction control
Reexamination Certificate
2000-04-25
2001-12-25
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
Shift direction control
C377S077000
Reexamination Certificate
active
06333959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the delay lock loop (DLL) circuit in a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and more particularly to the shift register portion of the DLL circuit.
2. State of the Art
In a synchronous dynamic random access memory (SDRAM) system, operations performed within the system, such as read or write operations, are clocked or synchronized to the rising and falling edge of an external system clock. In particular, in a double data rate (DDR) SDRAM system or device, data is clocked out of the device such that it is synchronized with both the rising and falling edge of the external clock. In order to implement this type of synchronization, a delay lock loop (DLL) circuit is used.
FIG. 1A
shows a system block diagram of a SDRAM
10
design including DLL circuitry
11
which in response to external clock
11
A provides an optimum delayed clock signal
11
B to the data output buffer
12
such that the data
12
A from the DRAM core
13
is output from the buffer
12
on the rising and falling edge of the external clock
11
A to provide Output Data signal
12
B.
FIG. 1B
shows a basic prior art digital DLL circuit
14
including an input receiver buffer
15
for receiving an external clock signal
15
A and providing an internal clock signal
15
B to a delay unit circuit
16
. The delay unit circuit
16
is programmably adjustable by a digital state stored within a shift register
17
to provide a variable time delay so as to generate a clock signal
16
A that corresponds to the internal clock signal
15
B delayed by the amount established within the delay unit circuit. Clock signal
16
A is used to clock output buffer
18
such that data from the DRAM core
18
A is clocked through buffer
18
on the subsequent rising and falling edges of the external clock signal
16
A. The DLL circuit further includes a feedback loop having a Phase Detector
19
which, depending on the phase difference between a feedback clock signal
16
A′ and the internal clock signal
15
B causes the shift register to shift left or right thereby increasing or decreasing, respectively, the delay value stored within shift register
17
. Dummy output buffer
20
and Dummy receiver buffer
21
provide a path for feedback Clk signal
16
A that is the equivalent to the path for the external clock signal
15
A. The delay value stored in register
17
is used to program delay unit circuit
16
such that data
18
A is clocked through buffer
18
to the output of the memory device on each of the next rising or falling edge of the external clock signal.
FIG. 1C
shows a typical prior art bi-directional shift register usable in the DLL circuit shown in FIG.
1
B. The shift register includes a plurality of clocked D-type flip-flops (FF
1
, FF
2
. . . FF(n)) and a plurality of multiplexers (MUX
1
, MUX
2
. . . MUX(n))—one coupled to the input of each latch. Each multiplexer passes data from the output of either the previous or next flip-flop within the shift register to the input of its corresponding flip-flop to perform either the right or left shift operation. The multiplexers pass the data dependent on the right and left shift control signals provided by the phase detector and coupled to the select input port (S) of each multiplexer in FIG.
1
C. The flip-flop is generally edge triggered by the clock signal (CLK) such that on a first clock cycle edge (either rising or falling), the next or previous data passed by the multiplexer is clocked into the flip-flop and on the second clock cycle edge (the same edge as the first cycle) the data is latched to the flip-flop output.
FIG. 1D
shows a one prior art design of a D type flip-flop typically used within the shift register shown in FIG.
1
C. The flip-flop is designed with two J-K edge-triggered flip flop latching stages—a master latch and a slave latch. As is well known in digital circuit design, latches are typically implemented with cross-coupled NAND gate circuits as shown in FIG.
1
D.
One problem which is encountered when designing a conventional DLL circuit using the shift register as shown in
FIG. 1C
implemented with the flip-flop as shown in
FIG. 1D
is that in order to cover a wide operating frequency range while maintaining an acceptable adjustment resolution a large number of individual delay unit elements and an equal number of flip-flops are required within the DLL circuit design. However, increasing the number of delay unit elements and flip-flops increases circuit complexity, size, and power consumption. Moreover, increased complexity, size, and power consumption results in an increase in noise inducement within the DLL circuit during operation and undesirable affects due to noise. For instance, jitter (i.e., signal shifting over time) within the DLL circuit strongly depends on noise coupling within the DLL circuit. Hence, a significant design consideration when designing a DLL circuit is the simplification of the shift register design within the DLL circuit.
What would be desirable is to reduce the complexity of the bi-directional shift register used within a DLL circuit so as to minimize circuit noise and silicon space consumption of the bi-directional shift register. Reducing shift register complexity also allows a more robust delay unit and shift register to be designed into the DLL circuit which can provide increased resolution and reliability.
SUMMARY OF THE INVENTION
A simplified single-latch circuit, a bi-directional shift register implemented with the simplified single-latch circuit thereof, and a delay lock loop (DLL) circuit implemented with a bi-directional shift register thereof is described. Since the bi-directional shift register is designed with a single-latch instead of the conventional dual-latch (i.e., master/slave latches) stage, the size and complexity of the shift register is greatly reduced as well as the noise generated within the DLL circuit.
In one embodiment, a single-latch circuit includes an input circuit portion implemented with a first MOS device having its gate coupled to a first shift control signal line, its source coupled to the output data provided from a previous single-latch circuit and its drain coupled to a first node. The input circuit portion also includes a second MOS device having its gate coupled to a second shift control signal line, its source coupled to the output data provided from a next single-latch circuit and its drain coupled to the first node. The first and second shift control signals cause one of the next and previous output data signals to be driven on the first node which corresponds to a data value to be shifted during a first half cycle of a clock signal. The input circuit portion also includes a positive feedback loop circuit coupled to the first node for holding the state of the data value to be shifted on the input node of a clocked latching circuit portion during the second half of the clock cycle once the first and second devices are disabled by the first and second shift control signals. During a second half cycle of the clock signal the latching circuit portion is clocked “on” and latches the data value to be shifted to the output of the single-latch circuit. The latching circuit portion further includes a second positive feedback loop circuit for holding the logic state of the shifted data value on the output of the single latch circuit once the latching circuit portion is disabled in the subsequent first half of the next clock signal cycle.
In one embodiment, a bi-directional shift register is implemented with a plurality of latching stages, each stage comprising a single-latch circuit having a first input port for receiving the inverse of a first shift control signal, a second input port for receiving a second shift control signal, a third input port for receiving output data from a previous latching stage in the bi-directional shift register, a fourth input port for receiving output data from a next latching stage in the bi-directional shift register, a first clock in
Lai Steven
Shieh Je-Hurn
Burns Doane Swecker & Mathis L.L.P.
Wambach Margaret R.
Winbond Electronics Corporation
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