Cross-coupled parity circuit with charging circuitry to improve

Details Cross-coupled parity circuit with charging circuitry to improve Cross-coupled parity circuit with charging circuitry to improve

1995-06-21

1996-02-06

Beausoliel, Jr., Robert W.

Excavating

371 491, G06F 1110, H03M 1300

Patent

active

054901561

ABSTRACT:
A parity circuit generates an output parity bit responsive to a plurality of data input bits. The parity circuit comprises a plurality of transistor stages coupled to the input bits and the output bit, the value of the input bits defining at least one charging path through the transistor stages. The charging path is coupled at first and second nodes to a power supply, such that the charging path is supplied with current at both ends, thereby increasing the responsiveness of the parity circuit.

REFERENCES:
patent: 4451922 (1984-05-01), Dearden et al.
patent: 4695744 (1987-09-01), Giordano
patent: 4816706 (1989-03-01), Dhong et al.
patent: 5023480 (1991-06-01), Gieseke et al.
"Principles of CMOS VLSI Design--A Systems Perspective", by Neil Weste and Kamran Eshraghian, Reprinted with Corrections Oct., 1985, pp. 332-334.

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