Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1997-04-15
2004-02-17
Ton, Dang (Department: 2666)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S427000
Reexamination Certificate
active
06693902
ABSTRACT:
The disclosed embodiments are directed to a method for the cross-connection of Synchronous Digital Hierarchy (SDH) signals. The disclosed embodiments are directed to a cross-connection architecture for implementing the method.
BACKGROUND OF THE INVENTION
The synchronous digital hierarchy (SDH) comprises quite a large entity to be very far advanced in order to transmit time division signals in the telecommunication network. The recommendation CCITT G.707 defines the signals of the first level synchronous transport module (STM-1) for SDH signals having a transmission rate of 155.520 Mbit/s. Other defined levels are STM-4 (633.080 Mbit/s) and STM-16 (2.488.320 Mbit/s). Higher levels are under study. The recommendations CCITT G.708 specify the STM-N (where N=1, 4, 16) frame structure. The basic STM-1 frame is composed of bytes (8 bits), of which there are 2430 including the control blocks; then an STM-1 frame transmits 63 subsystem containers (e.g. TU-1, Tributary Unit, which can contain a 2 Mbit/s signal of a common 30 channel PCM system). The STM-1 frames are repeated 8000 times each second, which is the same as in the subsystem; thus each byte of a frame forms a 64 kbit/s channel. The STM-N frames are combined into logical multiframes. The SDH signals or transport modules are formed by interleaving the bytes of the subsystem signals.
The concept of the digital cross connect was developed in order to ensure a flexible growth of the telecommunications networks and to ensure more developed traffic control modes. Cross connect systems (SDH) DXC (Digital Cross Connect, CCITT draft recommendations G.sdxc-1...-3) are also under development for the synchronous digital hierarchy. The SDH DXC is defined (informally abbreviated): ‘A digital SDH cross connect is a cross connect device having two or more interfaces at SDH rates (G.707) and being at least able to terminate a transmission section and to controllable, transparently connect and reconnect virtual containers (VC) between the interface ports’.
An SDH DXC can transmit traffic between different SDH levels and connect traffic between different signals. The use of the cross connect also includes a possibility for remote control of routing, initialization of reserve routes, connection from one signal to several signals (broadcasting), and so on. The connections are usually bothway connections.
The mentioned CCITT SDH recommendations try to define the logical function, i.e. a functional structure of devices, but they avoid the detailed structural description of the devices.
The digital cross connect has already been studied a long time in order to find an architecture which meets the optimal conditions. A structure which readily meets the conditions regarding capacity, non-blocking properties and implementation, is the TST (Time-Space-Time) structure, or the time-space-time cross connect, schematically shown in FIG.
1
. On the left in the figure there are the input signals I
1
. . . In (here STM-1 signals) and on the right there are the output signals O
1
...On. The time switches Ti
1
. . . Tin and To
1
. . . Ton on the input side and output side, respectively, change the byte positions (within a frame) within a signal. The central space switch S transmits a signal from one time switch to a signal directed to another time switch. In principle the time switches are memory elements and the space switch is composed of switch elements. According to prior art the cross connect is implemented as a module structure. The TST cross connect is also suited for very large cross connects, although then some problems arise when the system grows.
Usually the STM-1 signals are logically cross-connected on the basis of bytes through the TST switch. The byte based switching means that the actual connection is performed at the SDH TU-12 level, i.e. logically 2 Mbit/s streams are connected. The logical connection rate per STM-1 signal is about 155 Mbit/s both in the time switches and in the space switch.
The problem is primarily created by the space switch. When the capacity of the space switch is exceeded the expansion is quadratic. When for example the 16×16 basic module (16×16 STM-1) of the space switch according to
FIG. 2
becomes full, then the next step is 32×32, which is realized by four 16×16 basic modules. Problems caused by the quadratic expansion are i.a.:
a) the connectors: the addition of modules always leads to multiple signal interfaces, as is shown in the example of FIG.
3
. The number of connector pins increases, and sufficient physical connectors cannot be found anymore when we arrive at large space switches. Problems are not caused only by the number of pins, but also by cables, the physical strength of the printed boards, and so on;
b) thermal power: the expansion also causes multiple input/output driver circuits in the cross connect, whereby the power consumption within a module increases too much;
c) space/distance: the quadratic expansion in large cross connects causes problems regarding the available space and the data transmission rates and synchronization of the signals when the distances between the basic modules of the space switch increase considerably.
Further it must be observed that even a preparation for the expansion causes the disadvantages according to points a) and b) above, in other words, when we make preparations for a very large expansion, then the interfaces required by the expansion reduce the maximum capacity of the basic module, or the planned maximum capacity as such accelerates the quadratic expansion.
FIG. 3
illustrates the quadratic expansion in a situation where the space switch has to switch a quadruple number, or 64 input signals to 64 output signals. Then the required number of basic modules increases to 16.
SUMMARY OF THE INVENTION
The object of the invention is now to present for the cross-connection of SDH signals a method and an architecture realizing the method, with which the need for the quadratic expansion can be postponed to a much later point. The object is also to reduce the number of required space switch modules in large cross connects.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Thus in a conventional TST cross connect structure ‘packets’ or bytes comprising 8 consecutive bits are connected through the cross connect. For this byte or these 8 bits the space switch thus makes only one new connection at the beginning of the byte, and the rest of the time the bits are connected through the switch by the same routing (this is what happens logically thinking; in practice the bits of the byte may be rearranged and connected in some suitable form within the space switch). It could be said that in the conventional solution each byte ‘consumes’ the interface capacity of the space module, in other words the maximum number of signals in the module depends on the transmission capacity (the bit rate) and the number of pins in the connectors.
The implementation of the invention is based on the fact that the time slot of a byte is utilized more efficiently, or the logical unit (=byte) is divided into smaller parts, and the parts or the bits of the byte are transmitted in parallel form through the space switch. Then the capacity of the space switch is utilized more efficiently. The implementation is also based on the fact that then each bit can be switched through the space switch independently of the other bits in the byte.
Parallell bit processing as such is no novelty. For example digital central offices have used time-space-time switches, in which the bytes are switched in a parallel mode through the switch means. This however relates to the fully parallel processing of the bits in a 2 Mbit/s channel time slot, both through the time and the space switch, whereby all bits in the time slot (byte) are processed in parallel, and the byte is connected in parallel mode through the whole TST switch. The primary goal has been to reduce the operating rate of the switches, but the logical structure of processing of the byte was not concerned. (See e.g. J-H. Pasanen, R.
Anttalainen Tarmo
Lindholm Pentti
Sahlman Kari
Hogan & Hartson LLP
Marconi UK Intellectual Property Ltd.
Ton Dang
Tran Phuc
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