Cross clock domain clocking for a system using two clock frequen

Details Cross clock domain clocking for a system using two clock frequen Cross clock domain clocking for a system using two clock frequen

1997-09-26

1999-06-22

Heckler, Thomas M.

395556, G06F 106, G06F 112

Patent

active

059151072

ABSTRACT:
A processor includes a processing core that is operable at a frequency that is an odd half-integer multiple of a bus clock frequency. Signals on a system bus are synchronized with a selected edge, e.g., the rising edge, of a bus clock signal, but the processing core requires signals synchronized with a processor clock signal. Signal crossing between the clock domain of the processing core and the clock domain of the system bus pass through a storage element that selectably latches a value of the signal either at a rising edge or a falling edge of the processor clock signal. A control circuit selects either rising-edge or falling-edge latching depending on which edge (rising or falling) is closest to being synchronized with the selected edge of the bus clock signal.

REFERENCES:
patent: 5036230 (1991-07-01), Bazes
patent: 5371416 (1994-12-01), Atriss et al.
patent: 5450458 (1995-09-01), Price et al.
patent: 5634116 (1997-05-01), Singer

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