Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-03-22
2001-10-30
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S725000, C438S745000
Reexamination Certificate
active
06309976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and more particularly to masks for patterning semiconductor devices.
2. Description of Related Art
U.S. Pat. No. 5,798,303 of Clampitt for “Etching Method for Use in Fabrication of Semiconductor Devices” describes an oxygen plasma descum method using oxygen to remove a polymer material by etching using “a descum step
14
, such as, for example, an oxygen plasma descum, to selectively etch the blocking material from the substantially vertical sidewall of the device . . . ”, Col. 3, lines 54-65. Referring to Col. 5, 26-41, polymer blocking material
64
,
66
forms over sidewall spacers
46
/
52
during the removal of conductive material
60
which is not protected by the photoresist
62
. The blocking material
64
/
66
must be removed from the device. An inert carrier such as helium can be incorporated with the oxygen in the plasma. (Col. 6, lines 19-18.) A fluorine containing gas and oxygen plasma can be used (Col. 7, lines 7-17.)
U.S. Pat. No. 5,637,186 of Liu et al. for “Method and Monitor Testsite Pattern for Measuring Critical Dimension Openings” describes measurement of After Development Inspection (ADI) and After Etching Inspection (AEI) for layers of photoresist, see Col. 4, lines 49-67.
U.S. Pat. No. 4,800,251 of Matsuoka for “Apparatus for Forming a Resist Pattern” U.S. Pat. No. 5,200,360 of Bradbury et al. for “Method for Reducing Selectivity Loss in Selective Tungsten Deposition”, and U.S. Pat. No. 5,259,924 of Mathews et al. for “Integrated Circuit Fabrication Process to Reduce Critical Dimension During Etching” show plasma descum methods.
U.S. Pat. No. 4,529,860 of Robb for “Plasma Etching of Organic Materials” shows a plasma etching (descum) process.
U.S. Pat. No. 4,959,326 of Roman et al. for “Fabricating T-Gate MESFETS Employing Double Exposure, Double Develop Techniques” teaches a double exposure technique to improve photo accuracy.
SUMMARY OF THE INVENTION
The process of this invention provides a way to provide a critical dimension controlled method of descum for conventional quarter micron (0.25 &mgr;m) and smaller dimension (0.18 &mgr;m) binary mask manufacture.
This invention teaches a method to improve ASTRIPI (After STRIPping Inspection) target by adding an etch step depending on AEI (After Etching Inspection) measurement. The invention uses plasma descum that improves the CD (Critical Dimension).
We have found that it is possible to use a method of controlling the ASTRIPI mean value by an Adding Etching (AE) method which involves addition to the system of an isotropic etchant which etches away the mask material to etch away the sidewalls of openings in the mask as a function of time.
The adding etching (AE) method makes it necessary to estimate the Side Etching Value (SEV) so that the correct amount of material is removed from the sidewalls of the openings in the mask. Sidewall etching is a process in which an etching gas is added to the system to etch away unwanted sidewall material in the openings in the mask. The sidewall etching step is followed by an ASTRIPI (After STRIPping Inspection) step.
The value of a Side Etching Value (SEV) step depends on developing the pattern profile, the resistance thickness, the pattern density, the pattern tone, and the pattern critical dimensions.
Since the range of the Side Etching Value (SEV) which results from the SEV process is from about 50 nm to about 120 nm, it is difficult to decide what parameters will provide a suitable Adding Etching (AE) program. On the one hand too little side etching occurs. On the other hand too much side etching occurs and there is a problem of serious undercut.
An object of this invention is to reduce the error budget by eliminating the sidewall etching value estimated error.
A further object of this invention is to simplify the processing steps.
An object of this invention is to control the CD (Critical Dimension) mean value range well within ±20 nm of CD.
In accordance with this invention, a method is provided for forming a mask from a metal layer deposited upon a substrate patterned for exposure of a workpiece to radiation of a specific range of wavelengths with the substrate being transparent to the radiation comprises the following steps. Form the metal layer superjacent to the substrate. Form a photoresist layer superjacent to the metal layer. Expose the photoresist layer to a pattern. Develop the photoresist to Form a photoresist mask with an opening therethrough. Bake the photoresist mask, the metal layer and the substrate. Perform a descum operation. Perform an isotropic etching of the metal layer through the opening in the mask. Perform an after etching inspection measurement. Strip the photoresist mask. Perform an after stripping inspection measurement. The isotropic etching is performed with a wet etchant.
Preferably, the descum operation is performed with a dry plasma process including oxygen and nitrogen gases and an inert gas selected from argon and helium.
REFERENCES:
patent: 4529860 (1985-07-01), Robb
patent: 4800251 (1989-01-01), Matsuoka
patent: 4938839 (1990-07-01), Fujiumra et al.
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patent: 5380608 (1995-01-01), Miyashita et al.
patent: 5393374 (1995-02-01), Sato et al.
patent: 5637186 (1997-06-01), Liu et al.
patent: 5783099 (1998-07-01), Huh
patent: 5783366 (1998-07-01), Chen et al.
patent: 5798303 (1998-08-01), Clampitt
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patent: 55144247 (1980-11-01), None
patent: 55143560A (1980-11-01), None
patent: 58024143 A (1983-02-01), None
Yamazaki et al., Manufacture of Photomask, JP 55143560 A, English Abstract, 2 pages, Nov. 1980.*
Arii et al., Photomask, JP 58024143 A, English Abstract, 2 pages, Feb. 1983.*
Mitsubishi Electric Corp., Photomask preparation—by forming masking layer on glass base, applying polymeric layer, irradiating to evaporate polymer and form mask and etching, etc., JP 55144247 A, English Abstract, 2 pagesl, Nov. 1980.*
Wolf et al., Silicon Processing for the VLSI Era: vol. 1—Process Technology, Lattice Press, pp. 429, 449, and 484, 1986.
Duan Cheng-Lung
Lin Tzy-Ying
Tien Tsung-Wen
Ackerman Stephen B.
Jones II Graham S.
Kunemund Robert
Saile Geroge O.
Taiwan Semiconductor Manufacturing Company
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