Excavating
Patent
1997-03-12
1999-02-09
Gordon, Paul P.
Excavating
371 376, 371 53, G06F 1110
Patent
active
058704132
ABSTRACT:
When encoding, data bits in a CRC code word are received for every bit by a dividing circuit where the CRC code word is divided by a generation polynomial and a remainder is output from parallel data output terminals. The remainder is added to a CRC intrinsic value and "0" information in the adder. The addition result is a CRC code in a CRC code word for transmission. When a code error is detected, data bits in a CRC code word and a CRC code are received for every bit by the dividing circuit, where they are divided by the generation polynomial and a remainder is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder, and the result is further processed by a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.
REFERENCES:
patent: 4238852 (1980-12-01), Iga et al.
patent: 4630271 (1986-12-01), Yamada
patent: 4910736 (1990-03-01), Tanaka et al.
Kodama Yukio
Murakami Kazuo
Gordon Paul P.
Marc McDieunel
Mitsubishi Denki & Kabushiki Kaisha
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