CRC calculation apparatus having reduced output bus size

Details CRC calculation apparatus having reduced output bus size CRC calculation apparatus having reduced output bus size

1985-12-02

1988-01-19

Fleming, Michael R.

Excavating

G06F 1112

Patent

active

047208309

ABSTRACT:
There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a group clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant group of the checksum register. A group wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the groups of CRC data can be shifted into position through the array one group per each cycle of the group clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several different architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be peformed on all groups of a message while excluding some selected number of bits in the first group is also disclosed.

REFERENCES:
patent: 4216540 (1980-08-01), McSpadden
patent: 4360891 (1982-11-01), Branigin
patent: 4477903 (1984-10-01), Schouhamer et al.

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