Crater prevention technique for semiconductor processing

Details Crater prevention technique for semiconductor processing Crater prevention technique for semiconductor processing

1992-07-08

1994-05-31

Quach, T. N.

Fishing, trapping, and vermin destroying

437 69, 437189, 437228, 437241, H01L 2131, H01L 21283

Patent

active

053169760

ABSTRACT:
A semiconductor fabrication process is provided which prevents the cratering of the bond pads of an integrated circuit by including in a semiconductor process an etch stop layer which is formed between the field oxide layer and the first dielectric layer to prevent erosion of the field oxide while allowing etching and removal of the first dielectric layer to prevent cratering.

REFERENCES:
patent: 4810666 (1989-03-01), Taji
patent: 4916084 (1990-04-01), Shibata et al.
patent: 5094980 (1992-03-01), Shepela
"A Bond Failure Mechanism", T. Kock et al., IEEE/IRPS, pp. 55-60, 1986.
Bond Pad Structure Reliability, Ching et al, Texas Instruments, Inc. 1988 IEEE/IRPS, pp. 64-70.
Ghandri, S. K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 432-435.

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