Crack stops

Details Crack stops Crack stops

1998-12-22

2001-08-07

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C257S618000, C257S622000, C438S113000, C438S114000

Reexamination Certificate

active

06271578

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the fabrication of semiconductors and, more particularly, to reducing cracks and chips during wafer dicing.
BACKGROUND OF THE INVENTION
In semiconductor fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces, forming devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC). The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization. Such techniques are described in S. M. Sze,
VLSI Technology,
2nd ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes.
To increase throughput, a plurality of ICs are fabricated on a wafer in parallel. The ICs are then separated into individual chips. The process of separating the wafer into individual chips is typically referred to as “dicing.” Conventionally, various dicing techniques, such as “grind-cut” and “scribe and break”, are employed. Such conventional dicing techniques are described in U.S. Pat. No. 3,942,508 to Shimizo, which is herein incorporated by reference for all purposes.
Referring to
FIG. 1
, a portion of a wafer
100
is depicted. Illustratively, the wafer comprises ICs
114
and
115
separated by a channel
120
. Channel
120
is the area in which the dicing tool cuts or scribes to separate the ICs. The width of the channel is, for example, about 100 microns (&mgr;m). Typically, the channel is covered with a dielectric layer
121
, such as oxide. The surface of the wafer is covered with hard and soft passivation layers
124
and
125
, respectively. The hard passivation layer, for example, comprises silicon dioxide or silicon nitride and the soft passivation layer comprises polymide. The passivation layers serve to protect the surface of the ICs. Prior to wafer dicing, the passivation layers in the channel are typically removed, leaving a portion of the dielectric layer of the metallization.
As the dicing tool cuts or scribes the wafer, cracks and chips result. Due to the properties of the typical dielectric layer, cracks propagate from the area where the dicing tool cuts the wafer. Cracks in excess of a few microns in depth and several tenths of millimeters in length have been observed. In some instances, such cracks can extend from the cutting edge into the active chip areas, causing significant reliability degradation in the resulting ICs. This decreases the yield of ICs per wafer.
From the above discussion, it is apparent that there is a need to reduce the propagation of cracks and chips that result from dicing.
SUMMARY OF THE INVENTION
The invention relates to crack stops for reducing the severity of cracks resulting from dicing of a semiconductor wafer into a plurality of chips. In accordance with the invention, discontinuities in the thickness of the dielectric layer in the channel regions are created near the edges of the active regions of the ICs, separating the dicing and active chip areas. The discontinuities serve as crack stops by inhibiting the propagation of cracks into the active regions of the ICs. The discontinuities result in an increase and/or decrease in the thickness of the dielectric layer. The discontinuities are created as part of existing FEOL and/or BEOL processes with design modifications, such as changing the design of the lithographic masks used for these processes. As such, the formation of the crack stops does not require additional process steps. Thus, raw process time needed to fabricate the ICs is not increased while improving the yield of chips per wafer.


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