Crack detecting device for plasma display panel

Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device

Reexamination Certificate

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Details

C315S169300

Reexamination Certificate

active

06441561

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device and method of detecting glass cracks. More particularly, it relates to a device and method of detecting cracks in a plasma display panel (hereinafter referred to as PDP).
2. Description of the Related Art
FIG. 1
is a cross-sectional view of a single cell in a conventional PDP. The PDP includes a front substrate
1
, and a rear substrate
7
. The front substrate
1
has at least a sustaining electrode X, at least a scanning electrode Y which is parallel to the sustaining electrode X, a dielectric layer
3
, and a protective film
5
. The rear substrate
7
has at least one addressing electrode A and a fluorescent layer
9
. The addressing electrode A is perpendicular to the sustaining electrode X and the scanning electrode Y. Further, partition walls
8
are formed to isolate each PDP cell.
FIG. 2
is a block diagram illustrating a plasma display panel (PDP)
100
formed by the PDP cells shown in FIG.
1
. The PDP
100
is driven by the scanning electrodes Y
1
~Yn, the sustaining electrodes X
1
~Xn, and the addressing electrodes (not shown). Furthermore, the PDP
100
includes the control circuit
110
, the scanning driver (Y driver)
112
, the sustaining driver (X driver)
114
, and the addressing driver (not shown). The control circuit
110
generates timing signals for all drivers according to the external clock signal CLOCK, the data signal DATA, the vertical synchronous signal V
SYNC
, and the horizontal synchronous signal H
SYNC
. The clock signal CLOCK represents the data transmittal clock, and the data signal DATA represents the display data. The vertical synchronous signal V
SYNC
and the horizontal synchronous signal H
SYNC
are used to define the timing sequences of a single frame and a single scanning line, respectively. The control circuit
110
delivers the display data and the clock signal to the addressing driver, and also delivers the corresponding frame control clock via signal lines
102
to the scanning driver
112
and the sustaining driver
114
.
FIG. 3
is a diagram illustrating the driving method to display a single frame of the conventional PDP. As shown, each frame is divided into eight sub-fields SF
1
~SF
8
. Each sub-field has three periods including the reset period R
1
~R
8
, the address period A
1
~A
8
, and the sustain period S
1
~S
8
. In the reset period, the residual charges of the preceding sub-field is cleared and a small amount of the wall charges is produced in the present sub-field. During the address period, wall charges are accumulated in the displayed sub-field, in other words, it is used to “turn on” the sub-field. Further, discharging will be continued during the sustain period for displaying images. During the reset period R
1
~R
8
or the sustain period S
1
~S
8
, all of the sub-fields are processed at the same time. On the other hand, the address step is sequentially performed for each cell on the scanning electrodes Y
1
~Yn during the address period A
1
~A
8
. Moreover, the display brightness is proportional to the length of the sustain period S
1
~S
8
. In the example of
FIG. 3
, the length of the sustain periods S
1
~S
8
of the sub-fields SF
1
~SF
8
can be set in a ratio of 1:2:4:8:16:32:64:128 to display images in 256 gray scales.
FIG. 4
is a timing diagram of the control signals on sustaining electrodes X and scanning electrodes Y in a single sub-field of the prior art. The signals on the sustaining electrodes X are generated by the sustain driver
114
, and the signals on the scanning electrodes Y are generated by the scan driver
112
. As shown in the drawing, each sub-field includes the reset period, the address period and the sustain period. It should be noted that the waveform of driving signals shown in the drawing is only an example. The waveform varies in practice, but the same theory is applied.
A PDP is a device with electrodes driven by a high voltage (the voltage can reach around 200 volts). If the front substrate cracks to expose the electrodes (due to a sudden hit, for example), the user may get an electric shock. Therefore, it is necessary to design a device that can detect cracks on the substrate and stop the operating circuit.
A conventional way to detect a glass crack is disclosed. For example, in the common building, a detector is attached to the window and used to detect the glass crack and give an alarm. However, this kind of detector is too bulky to be applied on the thin PDP.
Accordingly, the present invention provides a plasma display panel with an elongated wire extended beyond both edges of the panel to carry a specified signal for detecting cracks. When a front substrate cracks, the specified signal is vanished. After a detect circuit detects the disappearance of the specified signal, the detect circuit will notify the control circuit to turn off the power. The wire can be positioned on the front substrate and be manufactured by the same step for forming other electrodes without resulting in extra manufacturing steps.
To achieve above-mentioned object, the invention provides a plasma display panel (PDP) having a plurality of pixels, a plurality of sustaining electrodes, and a plurality of scanning electrodes. When a bias is applied to the plurality of sustaining electrodes and the plurality of scanning electrodes, a discharge operation is performed in the plurality of pixels. The plasma display panel of the present invention includes: a front substrate having a first edge and a second edge in opposition to each other, a signal transmitter disposed on the first edge of the front substrate, a signal receiver disposed on the second edge of the front substrate, a detecting wire disposed on the front substrate, and a control circuit coupled to the signal transmitter and the signal receiver. The detecting wire has a first end and a second end, the first end is coupled to the signal transmitter, and the second end is coupled to the signal receiver. When the signal transmitter sends a detecting signal and the signal receiver doesn't receive the detecting signal, the control circuit interrupts the bias applied between the plurality of sustaining electrodes and the plurality of scanning electrodes so as to stop the discharge operation in the plurality of pixels.
The signal receiver sends a notifying signal to the control circuit when not receiving the detecting signal. The control circuit will turn off the power of the plasma display panel so as to stop the operation of the signal transmitter after receiving the notifying signal.
Moreover, the plasma display panel of the present invention further includes: a rear substrate positioned opposite to the front substrate and having a plurality of addressing electrodes, a dielectric layer covered the sustaining electrodes and the scanning electrodes, and a protective film covered the dielectric layer.
The present invention further provides another structure of the PDP that can detect glass cracks. In this embodiment, the detecting wires are not formed in the non-display area, instead, the detecting wires can be formed in the display area. Several specified display electrodes are extended from one edge of the substrate to another edge of the substrate to form the detecting wires. The signal transmitter can be replaced by a scan driver or a sustain driver for controlling the scanning electrodes or the sustaining electrodes. The driving signal of these drivers can be transmitted to the signal receiver through the detecting wire. The signal receiver can detect the state of the driving signals at a specified time for determining an open circuit cause by the crack of the glass substrate. If there is an open circuit on the detecting wire, the control circuit will be notified. The present invention can detect not only a glass crack but also an error waveform of the driving signal. Therefore, the self-testing function of the circuit is provided.


REFERENCES:
patent: 4326151 (1982-04-01), Weisbrod

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