CPU-Synchronous parallel data processor apparatus

Details CPU-Synchronous parallel data processor apparatus CPU-Synchronous parallel data processor apparatus

1976-11-29

1978-01-31

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 918, G06F 916

Patent

active

040718905

ABSTRACT:
At least one parallel processor (PP or P-P) is connected between a central processing unit (CPU) interface and main memory for processing certain data simultaneously and synchronously with operation of the CPU. Integrated circuit apparatus for implementing the functions performed by the PP includes an arithmetic and logic unit (ALU), a set of registers, microprogrammable circuitry (RAM's, ROM's, PROM's) and other integrated circuitry. The PP includes decode and control apparatus, which decodes microinstructions stored in an extension to the control store of the CPU, the extension forming part of the CPU/P-P interface, and thereafter employs the decoded microinstructions to control operation of the P-P.

REFERENCES:
patent: 3593299 (1971-07-01), Driscoll et al.
patent: 3713107 (1973-01-01), Barsamian
patent: 3902162 (1975-08-01), Parkinson et al.
patent: 3988717 (1976-10-01), Kisylia

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