CPU surge reduction and protection

Details CPU surge reduction and protection CPU surge reduction and protection

2008-05-20

2008-05-20

Sherry, Michael (Department: 2836)

Electrical transmission or interconnection systems

Combined impedance and switch systems

C307S052000, C307S103000

Reexamination Certificate

active

07375443

ABSTRACT:
Methods and systems of providing power to a central processing unit (CPU) provide for enhanced surge protection during CPU current consumption going from high current to low current consumption. In one approach, a circuit as a power output stage with an output node, and a controller circuit coupled to the power output stage. The controller circuit selectively switches the power output stage into a current ramp down mode based on detection of a voltage surge at the output node. The power output stage has an associated current ramp down rate. The CPU is coupled to the output node and a surge notification input of the power output stage, where the power output stage accelerates the current ramp down based on a notification signal from the CPU for a duration proportional to the change in CPU current consumption from high to low current consumption.

REFERENCES:
patent: 6188209 (2001-02-01), Poon et al.
patent: 6271651 (2001-08-01), Stratakos et al.
patent: 6285175 (2001-09-01), Massie

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