CPU reads data from slow bus if I/O devices connected to fast bu

Details CPU reads data from slow bus if I/O devices connected to fast bu CPU reads data from slow bus if I/O devices connected to fast bu

1997-03-27

1999-04-27

Luu, Le H.

395879, 395838, 395835, 395839, G06F 1300

Patent

active

058988947

ABSTRACT:
A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

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Bursky, Dave, "Memory -CPU Interface Speeds Up Data Transfers", Electronic Design, Mar. 19, 1992, pp. 137-142.

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