CPU programmable control system

Details CPU programmable control system CPU programmable control system

1973-09-04

1976-06-08

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06f 900

Patent

active

039626830

ABSTRACT:
A synchronous computing system includes a central processor unit interconnected with external memory units. The processor is integrated monolithically on a single chip and includes a plurality of data registers, a parallel arithmetic logic unit and an instruction register interconnected by a common parallel buss. A control section of the processor synchronizes internal operation of the processor and also system operation, and includes a plurality of programmable logic arrays to provide a versatile method of accommodating different instruction sets, sequences of operation, and instruction cycle duration. The arrays reduce the number of interconnects required and increases utilization of semiconductor material for forming active devices.

REFERENCES:
patent: 3453607 (1969-07-01), Cohler et al.
patent: 3528060 (1970-09-01), Streif
patent: 3537074 (1970-10-01), Stokes et al.
patent: 3564507 (1971-02-01), Faivre et al.
patent: 3566368 (1971-02-01), Blauw
patent: 3602900 (1971-08-01), Delaigue et al.
K. A. Duke, "Interval Timer"--IBM Technical Disclosure Bulletin, Dec. 1967.

Affiliated with

Also associated with

Rating

CPU programmable control system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CPU programmable control system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CPU programmable control system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1103335