CPU power management in non-APM systems

Details CPU power management in non-APM systems CPU power management in non-APM systems

1996-09-30

1998-12-01

An, Meng-Ai T.

39575006, 39575008, G06F 132

Patent

active

058451382

ABSTRACT:
In order to save power in a computer system which lacks an APM BIOS or similar built-in power management facility, a power management V.times.D is hooked into the idle callback chain in such a way that it is the last device driver to receive an idle callback. Upon receipt of an idle callback, the power management V.times.D causes the CPU to enter a low-power consumption state. For processors that support a halt state, this may be done by issuing a HLT instruction to the CPU. Control returns to the power management V.times.D upon subsequent occurrence of an external interrupt, after which the power management V.times.D consumes the idle and returns control to the operating system.

REFERENCES:
patent: 5560022 (1996-09-01), Dunstan et al.
patent: 5590342 (1996-12-01), Marisetty
patent: 5655126 (1997-08-01), Glenning

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