CPU pipeline having queuing stage to facilitate branch instructi

Details CPU pipeline having queuing stage to facilitate branch instructi CPU pipeline having queuing stage to facilitate branch instructi

1995-10-06

1998-04-07

Lim, Krisna

395392, 395393, G06F 930

Patent

active

057375623

ABSTRACT:
A pipelined microprocessor is provided with a queuing stage between an instruction fetch stage and an instruction decode stage to facilitate branch instructions and to receive instructions from the fetch stage when the decode stage is stalled. If a branch is incorrectly anticipated the queuing stage has nonbranch sequential instructions for the decode stage while the fetch stage is restarted at the nonbranch sequential instruction stream.

REFERENCES:
patent: 5325495 (1994-06-01), McLellan
patent: 5450555 (1995-09-01), Brown, III et al.
patent: 5471591 (1995-11-01), Edmondson et al.
patent: 5490255 (1996-02-01), Rawlinson et al.
patent: 5619664 (1997-04-01), Glew

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