CPU lock logic for corrected operation with a posted write array

Details CPU lock logic for corrected operation with a posted write array CPU lock logic for corrected operation with a posted write array

1992-12-30

1994-10-04

Shaw, Gareth D.

Boots, shoes, and leggings

395725, 395200, 364DIG1, 3642386, 36424291, 3642468, G06F 1300, G06F 1336

Patent

active

053534166

ABSTRACT:
A shared bus arbitration system is disclosed which provides logic allowing multiple processors to co-exist on a common bus. In the present invention, the host processor is isolated from the bus by a posted write array or write buffer. The arbitration system accepts bus lock and cycle signals when the processor writes a locked instruction to the posted write array and provides a bus lock signal to the bus when the locked instructions are written to the bus.

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