CPU expansive gradation of I/O interruption subclass recognition

Details CPU expansive gradation of I/O interruption subclass recognition CPU expansive gradation of I/O interruption subclass recognition

1991-08-29

1993-06-22

Richardson, Robert L.

G06F 1300

Patent

active

052222152

ABSTRACT:
A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

REFERENCES:
patent: 4564903 (1986-01-01), Guyette et al.

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