CPU datapipe architecture with crosspoint switch

Details CPU datapipe architecture with crosspoint switch CPU datapipe architecture with crosspoint switch

2011-03-01

2011-03-01

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07899857

ABSTRACT:
Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality of multi-stage signal processing modules, which may be two-staged modules. Each state, in turn, includes: at least one data manipulation module for manipulating the input signal; a crosspoint switch for facilitating the receipt and parallel distribution of an input signal/manipulated output signal; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. A given crosspoint switch may be programmed to interconnect data manipulation modules in “datapipe” fashion, which is to say via a specified number of parallel data pathways.

REFERENCES:
patent: 6539488 (2003-03-01), Tota et al.
patent: 6675187 (2004-01-01), Greenberger
patent: 7536431 (2009-05-01), Goren et al.
patent: 2003/0182336 (2003-09-01), Nielsen et al.

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