1993-12-29
1996-08-13
Kriess, Kevin A.
G06F 108
Patent
active
055465684
ABSTRACT:
The present invention relates to an apparatus and method for controlling a CPU clock in response to certain events with a system in order to conserve power usage. These events can be programmably enabled or disabled. The apparatus comprises a circuit for detecting enabled Stop Clock events requiring the CPU clock to temporarily cease operation. In combination therewith, the present invention includes a circuit for detecting enabled Stop Break events which are used to re-start the CPU clock. The present invention further comprises a Speedup circuitry to increase the CPU clock speed for enabled speedup events which are dependent on CPU clock speed.
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patent: 5175853 (1992-12-01), Kardach et al.
patent: 5369771 (1994-11-01), Gettel
patent: 5390350 (1995-02-01), Chung et al.
patent: 5392437 (1995-02-01), Matter et al.
patent: 5428765 (1995-06-01), Moore
patent: 5430881 (1995-07-01), Ikeda
Bland Patrick M.
Jackson Robert T.
Joshi Jayesh
Kardach James
Chavis John Q.
Intel Corporation
International Business Machines - Corporation
Kriess Kevin A.
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