CPU bus allocation control

Details CPU bus allocation control CPU bus allocation control

1991-10-15

1993-08-24

Chun, Debra A.

Boots, shoes, and leggings

364DIG1, 3642405, 3642426, 36424292, 3642706, G06F 13362

Patent

active

052396312

ABSTRACT:
An arbiter with first and second CPU timers is provided which advantageously allows measuring and controlling CPU bus ownership intervals via the arbiter. The first CPU timer, a running timer, specifies the total interval that the CPU is allocated the bus. The second time, an idle timer, specifies an interval which the CPU may own the bus without performing an operation. The arbiter uses these two timers to dynamically adjust and control CPU bus ownership.

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patent: 4373183 (1983-02-01), Means et al.
patent: 4543629 (1985-02-01), Carey et al.
patent: 4787041 (1988-11-01), Yount
patent: 5140680 (1992-08-01), Best
patent: 5170481 (1992-12-01), Begun et al.
Microprocessors-vol. 12, No. 3, Apr. 1988, London GB pp. 125-129.
F. Van der Wateren `Fast DMA Controller for the VME Bus`, p. 128, right column, line 7--line 19; FIG. 4.
Patent Abstracts of Japan, vol. 12, No. 323 (P-752) 2 Sep. 1988 and JP-A-63 085 955 (Toshiba Corp.) 16 Apr. 1988.

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