CPU architecture performing dynamic instruction scheduling at ti

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395390, 395392, 3642303, 3642318, 3642624, 364DIG1, G06F 938

Patent

active

056405880

ABSTRACT:
An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.

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patent: 5261063 (1993-11-01), Kohn et al.
patent: 5428810 (1995-06-01), Barkans et al.
patent: 5487156 (1996-01-01), Popescu et al.

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