Covered slit isolation between integrated circuit devices

Details Covered slit isolation between integrated circuit devices Covered slit isolation between integrated circuit devices

2000-10-13

2001-07-24

Booth, Richard (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S510000, C257S522000

Reexamination Certificate

active

06265754

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits (“ICs”) fabricated on semiconductor wafers and more particularly to electrically isolating adjacent devices of ICs from each other.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve the improvements in complexity and circuit density, i.e., the number of devices capable of being packed onto a given chip area, the size of the smallest device feature, also known as the device “geometry”, has gotten smaller with each generation of ICs. Currently, devices are being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs, but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility.
Shrinking device geometries have presented several issues to address. For example, devices on an IC are typically electrically isolated from each other. A variety of methods have evolved to accomplish this. Early bipolar ICs used depletion-region isolation between devices. These methods rely on essentially forming a reverse-biased isolation alley, or well, around each device or cell of the IC. A depletion-region isolation technique must allow for a large inactive area of the silicon surface between adjacent devices, which adversely affects IC packing densities. The consumption of chip area using this isolation technique became more pronounced as device geometries shrank and the area required for device isolation became a larger fraction of the total IC area.
Metal-oxide-semiconductor (“MOS”) devices do not require the same type of isolating structure as bipolar devices, and ICs having the highest component densities are fabricated with MOS technologies. On way of isolating two adjacent MOS devices is with the local oxidation of silicon (“LOCOS”) method. The LOCOS method relies on a relatively thick field oxide to be formed between devices. This thick field oxide reduces the chance that a conductive trace laying over the oxide will act as the gate of a parasitic transistor, linking one cell to another.
FIGS. 1A-1C
show simplified cross sections of a silicon wafer during a LOCOS process.
FIG. 1A
shows a silicon wafer
10
with an oxidation mask layer
12
that has been patterned to form a window
14
that exposes the silicon. The oxidation mask is typically made of silicon nitride that has been formed by a chemical vapor deposition (“CVD”) process. Ions may be implanted through the window
14
into the silicon wafer to form an isolation well
16
. Oxygen and water vapor diffuse very slowly through the silicon nitride layer, compared to their rate of diffusion through silicon dioxide. A pad layer
18
of silicon dioxide is frequently grown on the silicon wafer using thermal oxidation means to cushion the surface stress between the oxidation mask
12
and the silicon wafer to
FIG. 1B
shows the wafer after the field oxide growth step. A field oxide
20
is thermally grown, usually by a wet oxidation (steam) method. About 45% of the thermal field oxide growth is downward, and 55% is upward, the resulting layer of silicon oxide being thicker than the silicon it consumes. The oxidation mask layer
12
effectively prevents oxide from growing beneath it, although lateral diffusion of oxygen and steam, including diffusion along the pad layer
18
causes oxide to grow under the oxidation mask layer
12
.
The wedge
22
of field oxide that grows underneath the oxidation mask has been named a “bird's beak” because of its characteristic shape. The bird's beak is a lateral extension of the field oxide
20
into the active area
24
of a device.
FIG. 1C
shows the wafer after the oxidation mask and pad oxide layers have been stripped. Stripping the pad oxide typically etches away part of the bird's beak oxide, and may expose a portion
26
of the isolation well
16
. Subsequent processing, such as a nitric-hydrofluoric acid dip to remove polymer stringers following a polysilicon deposition and patterning process, may remove additional amounts of the bird's beak and further expose the isolation well.
Another technique for isolating devices on an IC is shallow trench isolation (“STI”).
FIGS. 2A-2C
are simplified cross sections of a silicon wafer being processed according to an STI method.
FIG. 2A
shows a silicon wafer
10
with a trench
20
formed in the silicon. Dry etching techniques are typically used to form the trench, which is about 0.5-0.8 microns deep.
FIG. 2B
shows the silicon wafer
10
with CVD oxide filling the trench
20
and covering the field
22
of the wafer. A planarizing layer
24
, for example of photoresist or spin-on glass, provides a flat surface
26
which may then be etched back with a technique, such as reactive ion etching, that etches the planarizing layer material and the CVD oxide material at the same rate.
FIG. 2C
shows the wafer
10
at the conclusion of the etchback step. To ensure that the CVD oxide is removed from the field
22
, the field oxide is overetched. This overetching removes some of the CVD oxide below the surface of the wafer, thus exposing a portion of a sidewall
28
of the active area trench
20
.
In either instance, the exposed portion of the isolation edge can cause at least two problems. First, the decrease in isolation width decreases the isolation between adjacent devices. Second, the gate oxide or tunnel oxide thickness at the exposed portion of the isolation edge is thinner than elsewhere, which may cause earlier breakdown. Therefore, it is desirable to provide an isolation structure that is not as susceptible to oxide loss at the edge of the field oxide due to subsequent processing.
From the above, it is seen that a technique for an improved integrated circuit device is highly desirable.
SUMMARY OF THE INVENTION
The present invention provides a technique, including a method and a device, for manufacturing an integrated circuit device. In an exemplary embodiment, the present invention provides a technique for isolating adjacent cells, or devices, in an integrated circuit such as a flash memory device.
In a specific embodiment, the present invention provides a novel method for producing an insulating region in a substrate. The method includes a step of forming a slit a semiconductor substrate, such as a silicon wafer or the like. A conformal dielectric layer is formed over the field of the substrate and the surfaces of the slit, including the edge of the slit. A capping layer is formed over the conformal dielectric layer, pinching off the slit to form a void. The capping layer is patterned to form a cap over the slit, particularly the edges of the slit covered by the conformal dielectric layer. In one embodiment, the integrated circuit is a flash EEPROM and the conformal dielectric layer serves as the tunneling dielectric layer for the floating gate of the memory cell.
The present isolation structure provides reliability for fabrication techniques which often require extensive etching (e.g., wet or dry), which often damages field isolation layers made using conventional techniques. The present invention also provides an efficient isolation structure between a high voltage region, which may be on the periphery of an integrated circuit, and a main cell region such as those for flash memory cells.
These and other embodiments of the present invention, as well as its advantages and features are described in more detail in conjunction with the text below and attached figures.


REFERENCES:
patent: 5868870 (1999-02-

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